Girish Pahwa
According to our database1,
Girish Pahwa
authored at least 8 papers
between 2016 and 2021.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis OtherLinks
On csauthors.net:
Bibliography
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
2020
Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance.
IEEE Access, 2018
2016
Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X ION using compact modeling approach.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016