Victor M. van Santen

According to our database1, Victor M. van Santen authored at least 24 papers between 2014 and 2022.

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Bibliography

2022
FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2022

On the Reliability of FeFET On-Chip Memory.
IEEE Trans. Computers, 2022

2021
Minimizing Excess Timing Guard Banding Under Transistor Self-Heating Through Biasing at Zero-Temperature Coefficient.
IEEE Access, 2021

Reliability-Driven Voltage Optimization for NCFET-based SRAM Memory Banks.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

Special Session: Machine Learning for Semiconductor Test and Reliability.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

Self-Heating Effects from Transistors to Gates.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021

2020
On the Workload Dependence of Self-Heating in FinFET Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

BTI and HCD Degradation in a Complete 32 × 64 bit SRAM Array - including Sense Amplifiers and Write Drivers - under Processor Activity.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Modeling Emerging Technologies using Machine Learning: Challenges and Opportunities.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Impact of Self-Heating on Performance, Power and Reliability in FinFET Technology.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

NCFET to Rescue Technology Scaling: Opportunities and Challenges.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Modeling the Interdependences Between Voltage Fluctuation and BTI Aging.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Modeling and Evaluating the Gate Length Dependence of BTI.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Modeling and Mitigating Time-Dependent Variability From the Physical Level to the Circuit Level.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Reliability Challenges with Self-Heating and Aging in FinFET Technology.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

2018
Reliability in Super- and Near-Threshold Computing: A Unified Model of RTN, BTI, and PV.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Weighted time lag plot defect parameter extraction and GPU-based BTI modeling for BTI variability.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

Reliability Estimations of Large Circuits in Massively-Parallel GPU-SPICE.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Estimating and optimizing BTI aging effects: from physics to CAD.
Proceedings of the International Conference on Computer-Aided Design, 2018

2017
Interdependencies of Degradation Effects and Their Impact on Computing.
IEEE Des. Test, 2017

2016
Aging-aware voltage scaling.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Designing guardbands for instantaneous aging effects.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Connecting the physical and application level towards grasping aging effects.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014
Towards interdependencies of aging mechanisms.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014


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