Hao Jiang
Orcid: 0000-0003-2337-2539Affiliations:
- University of Science and Technology of China, School of Microelectronics, Hefei, China
- Chinese Academy of Sciences, Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Beijing, China
- Fudan University, State Key Laboratory of Integrated Chips and Systems, Frontier Institute of Chip and System, Shanghai, China
According to our database1,
Hao Jiang
authored at least 14 papers
between 2021 and 2025.
Collaborative distances:
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Bibliography
2025
Resistive memory-based zero-shot liquid state machine for multimodal event data learning.
Nat. Comput. Sci., January, 2025
2024
A Scalable Area-Efficient Low-Delay Asynchronous AER Circuits Design for Neuromorphic Chips.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2024
HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer.
IEEE Trans. Very Large Scale Integr. Syst., February, 2024
High-efficient and Comprehensive Modeling of MFIM Ferroelectric Tunnel Junctions for Non-volatile/Volatile Applications.
Proceedings of the IEEE International Memory Workshop, 2024
A 28nm 76.25TOPS/W RRAM/SRAM-Collaborative CIM Fine-Tuning Accelerator with RRAM-Endurance/Latency-Aware Weight Allocation for CNN and Transformer.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
2023
Multicore Spiking Neuromorphic Chip in 180-nm With ReRAM Synapses and Digital Neurons.
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023
Random resistive memory-based deep extreme point learning machine for unified visual processing.
CoRR, 2023
Resistive memory-based zero-shot liquid state machine for multimodal event data learning.
CoRR, 2023
A Scalable Die-to-Die Interconnect with Replay and Repair Schemes for 2.5D/3D Integration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A $2.53 \mu \mathrm{W}/\text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
TiPU: A Spatial-Locality-Aware Near-Memory Tile Processing Unit for 3D Point Cloud Neural Network.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021