Harry Chuang

According to our database, Harry Chuang authored at least 11 papers between 2018 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

Design-Technology-Reliability Co-Optimization for MRAM-OTP Integration - A Methodological Approach.

Y. C. Ong, Y. H. Chen, H. H. Wang, J. Q. Liang, Y. S. Chen, Jarcle Huang, T. W. Chiang, J. C. Huang, C. H. Weng, C. Y. Wang, Bruce P. H. Lee, Allen Y. J. Wang, K. C. Huang, Harry Chuang

Proceedings of the IEEE International Reliability Physics Symposium, 2025

Failure Mechanism and Unified Endurance Model of Embedded MRAM Towards Cache Application.

Y. H. Chen, Yu-Sheng Chen, Yi Ching Ong, Y. L. Chu, Kuo-Feng Huang, Yuan-Jen Lee, C. Y. Wang, C. Y. Wu, W. H. Chuang, Allen Y. J. Wang, K. C. Huang, Harry Chuang

Proceedings of the IEEE International Reliability Physics Symposium, 2025

2024

A Novel Phase Change Material RF Switch with 16nm Technology to Achieve Low Voltage and Low Ron*Coff for mmWave.

H. J. Li, K. P. Chang, C. E. Chen, W. T. Hsieh, H. H. Kuo, C. C. Huang, H. C. Chen, Z. H. Ya, H. Y. Chen, J. D. Jin, S. H. Yang, Y. W. Ting, K. C. Tseng, K. C. Huang, Harry Chuang

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 10¹² Write Endurance and Integrated Margin-Expansion Schemes.

Ku-Feng Lin, Hiroki Noguchi, Yi-Chun Shih, Perng-Fei Yuh, Yuan-Jen Lee, Tung-Cheng Chang, Sheng-Po Huang, Yu-Fan Lin, Chun-Ying Lee, Yen-Hsiang Huang, Jui-Che Tsai, Saman Adham, Peter Noel, Ramin Yazdi, Marat Gershoig, YangJae Shin, Vineet Joshi, Ted Wong, Meng-Ru Jiang, J. J. Wu, Chun-Tai Cheng, Yu-Jen Wang, Harry Chuang, Yu-Der Chih, Yih Wang, Tsung-Yung Jonathan Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

15.7 A 32Mb RRAM in a 12nm FinFet Technology with a 0.0249μm² Bit-Cell, a 3.2GB/S Read Throughput, a 10KCycle Write Endurance and a 10-Year Retention at 105°C.

Yi-Cheng Huang, Shang-Hsuan Liu, Hsu-Shun Chen, Hsin-Chang Feng, Chih-Feng Li, Chou-Ying Yang, Wei-Keng Chang, Chang-Feng Yang, Chun-Yu Wu, Yen-Cheng Lin, Tsung-Tse Yang, Chih-Yang Chang, Wen-Ting Chu, Harry Chuang, Yih Wang, Yu-Der Chih, Tsung-Yung Jonathan Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023

A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity.

Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih, Hon-Jarn Lin, Yen-An Chang, Cheng-Han Lu, Yu-Lin Chen, Chieh-Pu Lo, Chung-Chieh Chen, Cheng-Hsiung Kuo, Tan-Li Chou, Chia-Yu Wang, J. J. Wu, Roger Wang, Harry Chuang, Yih Wang, Yu-Der Chih, Tsung-Yung Jonathan Chang

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2020

A 22nm 96KX144 RRAM Macro with a Self-Tracking Reference and a Low Ripple Charge Pump to Achieve a Configurable Read Window and a Wide Operating Voltage Range.

Chung-Cheng Chou, Zheng-Jun Lin, Chien-An Lai, Chin-I Su, Pei-Ling Tseng, Wei-Chi Chen, Wu-Chin Tsai, Wen-Ting Chu, Tong-Chern Ong, Harry Chuang, Yu-Der Chih, Tsung-Yung Jonathan Chang

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

13.3 A 22nm 32Mb Embedded STT-MRAM with 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150°C and High Immunity to Magnetic Field Interference.

Yu-Der Chih, Yi-Chun Shih, Chia-Fu Lee, Yen-An Chang, Po-Hao Lee, Hon-Jarn Lin, Yu-Lin Chen, Chieh-Pu Lo, Meng-Chun Shih, Kuei-Hung Shen, Harry Chuang, Tsung-Yung Jonathan Chang

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019

Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub- $\mu$ A Sensing Resolution, and 17.5-nS Read Access Time.

Yi-Chun Shih, Chia-Fu Lee, Yen-An Chang, Po-Hao Lee, Hon-Jarn Lin, Yu-Lin Chen, Ku-Feng Lin, Ta-Ching Yeh, Hung-Chang Yu, Harry Chuang, Yu-Der Chih, Tsung-Yung Jonathan Chang

IEEE J. Solid State Circuits, 2019

Recent Progress and Next Directions for Embedded MRAM Technology.

William J. Gallagher, Eric Chien, Tien-Wei Chiang, Jian-Cheng Huang, Meng-Chun Shih, C. Y. Wang, Christine Bair, George Lee, Yi-Chun Shih, Chia-Fu Lee, Roger Wang, Kuei-Hung Shen, J. J. Wu, Wayne Wang, Harry Chuang

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018

Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time.

Yi-Chun Shih, Chia-Fu Lee, Yen-An Chang, Po-Hao Lee, Hon-Jarn Lin, Yu-Lin Chen, Ku-Feng Lin, Ta-Ching Yeh, Hung-Chang Yu, Harry Chuang, Yu-Der Chih, Tsung-Yung Jonathan Chang

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018