Harry Foster

According to our database1, Harry Foster authored at least 27 papers between 2001 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Report on the Design Automation Conference (DAC 2021).
IEEE Des. Test, 2022

2021
General Chair's Message.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2018
2018 FPGA Functional Verification Trends.
Proceedings of the 19th International Workshop on Microprocessor and SOC Test and Verification, 2018

2015
Trends in functional verification: a 2014 industry study.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2013
Keynote talk III: Industry pulse: Trends in function verification.
Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013

Why the design productivity gap never happened.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2010
Increasing the Efficiency of Simulation-Based Functional Verification Through Unsupervised Support Vector Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Bridging pre-silicon verification and post-silicon validation.
Proceedings of the 47th Design Automation Conference, 2010

2009
Applied Assertion-Based Verification: An Industry Perspective.
Found. Trends Electron. Des. Autom., 2009

Pain, Possibilities, and Prescriptions Industry Trends in Advanced Functional Verification.
Proceedings of the Hardware and Software: Verification and Testing, 2009

2008
Functional test selection based on unsupervised support vector analysis.
Proceedings of the 45th Design Automation Conference, 2008

Assertion-Based Verification: Industry Myths to Realities (Invited Tutorial).
Proceedings of the Computer Aided Verification, 20th International Conference, 2008

2007
Panel: Unified approach leading to a seamlessly evolving test bench for all phases of a multi-core design, validation and production test.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

2006
Panel: Assertion-Based Verification -What's the Big Deal?
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

Building a verification test plan: trading brute force for finesse.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Are Today's Verification Tools Able to Handle Current Design Challenges?
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Is methodology the highway out of verification hell?
Proceedings of the 42nd Design Automation Conference, 2005

2004
Exception handling in microprocessors using assertion libraries.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Panel: Driving the intelligent testbanch: are we there yet?
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

Assertion-based design, Second Edition.
Kluwer, ISBN: 978-1-4020-8027-2, 2004

2003
The Chip is Ready. Am I done? On-chip Verification using Assertion Processors.
Proceedings of the IFIP VLSI-SoC 2003, 2003

On-Chip Property Verification Using Assertion Processors.
Proceedings of the VLSI-SOC: From Systems to Chips, 2003

Refactoring digital hardware designs with assertion libraries.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

2002
Formal verification methods: getting around the brick wall.
Proceedings of the 39th Design Automation Conference, 2002

2001
Applied Boolean Equivalence Verification and RTL Static Sign-Off.
IEEE Des. Test Comput., 2001

Optimizing Multiple EDA Tools within the ASIC Design Flow.
IEEE Des. Test Comput., 2001

Principles of verifiable RTL design - a functional coding style supporting verification processes in Verilog.
Kluwer, ISBN: 978-0-7923-7368-1, 2001


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