Hongsik Jeong

According to our database1, Hongsik Jeong authored at least 12 papers between 1999 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A PRAM-based PIM Macro Using the Gilbert Multiplier-based Active Feedback and Input-aware SAR ADC.
Proceedings of the 20th International SoC Design Conference, 2023

2016
Modeling of data retention statistics of phase-change memory with confined- and mushroom-type cells.
Microelectron. Reliab., 2016

High density PCM(phase change memory) technology.
Proceedings of the International SoC Design Conference, 2016

2015
Emulation of spike-timing dependent plasticity in nano-scale phase change memory.
Neurocomputing, 2015

2008
A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput.
IEEE J. Solid State Circuits, 2008

2007
A 0.1-µm 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation.
IEEE J. Solid State Circuits, 2007


2006
Enhanced write performance of a 64-mb phase-change random access memory.
IEEE J. Solid State Circuits, 2006

2005
A 0.18-μm 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM).
IEEE J. Solid State Circuits, 2005

Emerging memory technologies.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2003
A 0.24-μm 2.0-V 1T1MTJ 16-kb nonvolatile magnetoresistance RAM with self-reference sensing scheme.
IEEE J. Solid State Circuits, 2003

1999
A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM.
IEEE J. Solid State Circuits, 1999


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