Hubert Kaeslin

According to our database, Hubert Kaeslin authored at least 51 papers between 1986 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

Towards Edge-Aware Spatio-Temporal Filtering in Real-Time.

Michael Schaffner, Florian Scheidegger, Lukas Cavigelli, Hubert Kaeslin, Luca Benini, Aljosa Smolic

IEEE Trans. Image Process., 2018

2016

Hybrid ASIC/FPGA System for Fully Automatic Stereo-to-Multiview Conversion Using IDW.

Michael Schaffner, Frank K. Gürkaynak, Pierre Greisen, Hubert Kaeslin, Luca Benini, Aljosa Smolic

IEEE Trans. Circuits Syst. Video Technol., 2016

2015

Semiconductor Technology and the Energy Efficiency of ICT.

Hubert Kaeslin

Proceedings of the ICT Innovations for Sustainability, 2015

Automatic multiview synthesis - Prototype demo.

Michael Schaffner, Frank K. Gürkaynak, Hubert Kaeslin, Luca Benini, Aljosa Smolic

Proceedings of the 2015 Visual Communications and Image Processing, 2015

Automatic multiview synthesis - Towards a mobile system on a chip.

Michael Schaffner, Frank K. Gürkaynak, Hubert Kaeslin, Luca Benini, Aljosa Smolic

Proceedings of the 2015 Visual Communications and Image Processing, 2015

2014

Dynamic memory-based physically unclonable function for the generation of unique identifiers and true random numbers.

Christoph Keller, Frank K. Gürkaynak, Hubert Kaeslin, Norbert Felber

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

An Approximate Computing Technique for Reducing the Complexity of a Direct-Solver for Sparse Linear Systems in Real-Time Video Processing.

Michael Schaffner, Frank K. Gürkaynak, Aljoscha Smolic, Hubert Kaeslin, Luca Benini

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

SIR10US: A tightly coupled elliptic-curve cryptography co-processor for the OpenRISC.

Michael Gautschi, Michael Muehlberghuber, Andreas Traber, Sven Stucki, Matthias Baer, Renzo Andri, Luca Benini, Beat Muheim, Hubert Kaeslin

Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013

Evaluation and FPGA Implementation of Sparse Linear Solvers for Video Processing Applications.

Pierre Greisen, Marian Runo, Patrice Guillet, Simon Heinzle, Aljoscha Smolic, Hubert Kaeslin, Markus H. Gross

IEEE Trans. Circuits Syst. Video Technol., 2013

A real-time 720p feature extraction core based on Semantic Kernels Binarized.

Michael Schaffner, Pascal Hager, Lukas Cavigelli, Pierre Greisen, Frank K. Gürkaynak, Hubert Kaeslin

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

A Complete Real-Time Feature Extraction and Matching System Based on Semantic Kernels Binarized.

Michael Schaffner, Pascal A. Hager, Lukas Cavigelli, Z. Fang, Pierre Greisen, Frank K. Gürkaynak, Aljoscha Smolic, Hubert Kaeslin, Luca Benini

Proceedings of the VLSI-SoC: At the Crossroads of Emerging Trends, 2013

Live demonstration: Real-time audio restoration using sparse signal recovery.

David E. Bellasi, Patrick Maechler, Andreas Burg, Norbert Felber, Hubert Kaeslin, Christoph Studer

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warping.

Michael Schaffner, Pierre Greisen, Simon Heinzle, Frank K. Gürkaynak, Hubert Kaeslin, Aljoscha Smolic

Proceedings of the ESSCIRC 2013, 2013

2012

Analysis and VLSI Implementation of EWA Rendering for Real-Time HD Video Applications.

Pierre Greisen, Michael Schaffner, Simon Heinzle, Marian Runo, Aljoscha Smolic, Andreas Burg, Hubert Kaeslin, Markus H. Gross

IEEE Trans. Circuits Syst. Video Technol., 2012

VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing.

Patrick Maechler, Christoph Studer, David E. Bellasi, Arian Maleki, Andreas Burg, Norbert Felber, Hubert Kaeslin, Richard G. Baraniuk

IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Hardware-efficient random sampling of fourier-sparse signals.

Patrick Maechler, Norbert Felber, Hubert Kaeslin, Andreas Burg

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

High-speed compressed sensing reconstruction on FPGA using OMP and AMP.

Lin Bai, Patrick Maechler, Michael Muehlberghuber, Hubert Kaeslin

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Compressive sensing for WiFi-based passive bistatic radar.

Patrick Maechler, Norbert Felber, Hubert Kaeslin

Proceedings of the 20th European Signal Processing Conference, 2012

Sparsity-based real-time audio restoration.

Patrick Maechler, David E. Bellasi, Andreas Burg, Norbert Felber, Hubert Kaeslin, Christoph Studer

Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2008

Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers.

Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner

IEEE Trans. Very Large Scale Integr. Syst., 2008

Gram-Schmidt-based QR decomposition for MIMO detection: VLSI implementation and comparison.

Peter Luethi, Christoph Studer, Sebastian Duetsch, Eugen Zgraggen, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

A hardware architecture for surface splatting.

Tim Weyrich, Simon Heinzle, Timo Aila, Daniel Bernhard Fasnacht, Stephan Oetiker, Mario Botsch, Cyril Flaig, Simon Mall, Kaspar Rohrer, Norbert Felber, Hubert Kaeslin, Markus H. Gross

ACM Trans. Graph., 2007

A 0.25 μm 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communication.

Flavio Carbognani, Simon Haene, Manuel Arrigo, Claudio Pagnamenta, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

42% power savings through glitch-reducing clocking strategy in a hearing aid application.

Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Two-phase resonant clocking for ultra-low-power hearing aid applications.

Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm.

Felix Bürgin, Flavio Carbognani, Martin Hediger, Hektor Meier, Robert Meyer-Piening, Rafael Santschi, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner

Proceedings of the 43rd Design Automation Conference, 2006

GALS at ETH Zurich: Success or Failure.

Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner

Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006

2005

Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC.

Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner

Proceedings of the Second Workshop on Globally Asynchronous, Locally Synchronous Design, 2005

Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications.

Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner

Proceedings of the Integrated Circuit and System Design, 2005

Improving DPA security by using globally-asynchronous locally-synchronous systems.

Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner

Proceedings of the 31st European Solid-State Circuits Conference, 2005

A 0.67-mm² 45-μW DSP VLSI implementation of an adaptive directional microphone for hearing aids.

Flavio Carbognani, Felix Bürgin, Luca Henzen, Herbert Koch, Hovig Magdassian, Christoph Pedretti, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004

A 2 Gb/s balanced AES crypto-chip implementation.

Frank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, Franco Hug, Hubert Kaeslin

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Towards an AES crypto-chip resistant to differential power analysis.

Norbert Pramstaller, Frank K. Gürkaynak, Simon Haene, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner

Proceedings of the 33rd European Solid-State Circuits Conference, 2004

2003

Waveform coding for low-power digital filtering of speech data.

Jürgen Wassner, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner

IEEE Trans. Signal Process., 2003

Variable delay ripple carry adder with carry chain interrupt detection.

Andreas Burg, Frank K. Gürkaynak, Hubert Kaeslin, Wolfgang Fichtner

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems.

Thomas Villiger, Hubert Kaeslin, Frank K. Gürkaynak, Stephan Oetiker, Wolfgang Fichtner

Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003

2002

2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis.

Adrian K. Lutz, Jürg Treichler, Frank K. Gürkaynak, Hubert Kaeslin, Gérard Basler, Antonia Erni, Stephan Reichmuth, Pieter Rommens, Stephan Oetiker, Wolfgang Fichtner

Proceedings of the Cryptographic Hardware and Embedded Systems, 2002

A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems.

Thomas Villiger, Stephan Oetiker, Frank K. Gürkaynak, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner

Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

2001

Design and Verification of a Stack Processor Virtual Component.

Manfred Stadler, Markus Thalmann, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner

IEEE Micro, 2001

2000

A new paradigm for very flexible SONET/SDH IP-modules.

Thomas Roewer, Manfred Stadler, Markus Thalmann, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999

Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor.

Manfred Stadler, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, Markus Thalmann

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1997

The impact of transistor sizing on power efficiency in submicron CMOS circuits.

Robert Rogenmoser, Hubert Kaeslin

IEEE J. Solid State Circuits, 1997

1996

Stochastic Methods for Transistor Size Optimization of CMOS VLSI Circuits.

Robert Rogenmoser, Hubert Kaeslin, Tobias Blickle

Proceedings of the Parallel Problem Solving from Nature, 1996

1994

A 177 Mb/s VLSI implementation of the International Data Encryption Algorithm.

Reto Zimmermann, Andreas Curiger, Heinz Bonnenberg, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner

IEEE J. Solid State Circuits, March, 1994

1993

VINCI: Secure Test of a VLSI High-Speed Encryption System.

Heinz Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, Reto Zimmermann, Wolfgang Fichtner

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

1991

VLSI Implementation of a New Block Cipher.

Heinz Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, Xuejia Lai

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1989

Architectural design and realization of a single-chip Viterbi decoder.

Marc Biver, Hubert Kaeslin, Carlo Tommasini

Integr., 1989

1988

Behandlung der Umlaute bei der Verarbeitung deutscher Texte unter UNIX / How to Handle German Umlauts when Processing Documents under UNIX.

Hubert Kaeslin

it Inf. Technol., 1988

Application of Graph Theory to Topology Generation for Logic Gates.

Hubert Kaeslin

Proceedings of the Graph-Theoretic Concepts in Computer Science, 1988

1986

A systematic approach to the extraction of diphone elements from natural speech.

Hubert Kaeslin

IEEE Trans. Acoust. Speech Signal Process., 1986

A comparative study of the steady-state zones of German phones using centroids in the LPC parameter space.

Hubert Kaeslin

Speech Commun., 1986