Gokul Krishnan

Orcid: 0000-0003-1813-1140

According to our database1, Gokul Krishnan authored at least 24 papers between 2013 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2023
SpikeSim: An End-to-End Compute-in-Memory Hardware Evaluation Tool for Benchmarking Spiking Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Artificial intelligence in clinical medicine: catalyzing a sustainable global healthcare paradigm.
Frontiers Artif. Intell., February, 2023

3D-ISC: A 65nm 3D Compatible In-Sensor Computing Accelerator with Reconfigurable Tile Architecture for Real-Time DVS Data Compression.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2022
Efficient continual learning at the edge with progressive segmented training.
Neuromorph. Comput. Eng., December, 2022

Hybrid RRAM/SRAM in-Memory Computing for Robust DNN Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Exploring Model Stability of Deep Neural Networks for Reliable RRAM-Based In-Memory Acceleration.
IEEE Trans. Computers, 2022

Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks.
ACM J. Emerg. Technol. Comput. Syst., 2022

COIN: Communication-Aware In-Memory Acceleration for Graph Convolutional Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Big-Little Chiplets for In-Memory Acceleration of DNNs: A Scalable Heterogeneous Architecture.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2021
SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks.
ACM Trans. Embed. Comput. Syst., 2021

Robust RRAM-based In-Memory Computing in Light of Model Stability.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

SWIFT: Small-World-based Structural Pruning to Accelerate DNN Inference on FPGA.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

System-Level Benchmarking of Chiplet-based IMC Architectures for Deep Neural Network Acceleration.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020
A Latency-Optimized Reconfigurable NoC for In-Memory Acceleration of DNNs.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020

Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs.
IEEE Des. Test, 2020

MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Accurate Inference with Inaccurate RRAM Devices: Statistical Data, Model Transfer, and On-line Adaptation.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Structural Pruning in Deep Neural Networks: A Small-World Approach.
CoRR, 2019

Towards Efficient Neural Networks On-a-chip: Joint Hardware-Algorithm Approaches.
CoRR, 2019

2014
Learning Integrated STEM Using Tangible Agent-Based Modeling.
Proceedings of the Learning and Becoming in Practice: Proceedings of the 11th International Conference of the Learning Sciences, 2014

Mathematical Machines and Integrated Stem: An Intersubjective Constructionist Approach.
Proceedings of the Computer Supported Education - 6th International Conference, 2014

Integrated STEM in Elementary Grades Using Distributed Agent-based Computation.
Proceedings of the CSEDU 2014, 2014

Independent N and P process monitors for body bias based process corner correction.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013


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