Pragnya Sudershan Nalla

According to our database, Pragnya Sudershan Nalla authored at least 9 papers between 2023 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

vFPGA: Towards Sub-µs Reconfiguration via 3D FPGA and Packaging Co-Design.

Nikhil K. Cherukuri, Sharad Nag, Pragnya Sudershan Nalla, Ashish K. Kola, Chetan S. Gadireddi, Kevin Dai, Jae-sun Seo, Zhenman Fang, Jeff Zhang, Yu Cao

Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2026

Chiplet-NAS: Chiplet-aware Neural Architecture Search for Efficient AI Inference on 2.5D Integration.

Cheng Guo, Pragnya Sudershan Nalla, Nikhil K. Cherukuri, Rui Xue, Sachin S. Sapatnekar, Chaitali Chakrabarti, Yu Cao, Jeff Zhang

Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025

Tiny Chiplets Enabled by Packaging Scaling: Opportunities in ESD Protection and Signal Integrity.

Emad Haque, Pragnya Sudershan Nalla, Jeff Zhang, Sachin S. Sapatnekar, Chaitali Chakrabarti, Yu Cao

CoRR, November, 2025

HISIM: Analytical Performance Modeling and Design Space Exploration of 2.5D/3D Integration for AI Computing.

Zhenyu Wang, Pragnya Sudershan Nalla, Jingbo Sun, A. Alper Goksoy, Sumit K. Mandal, Jae-Sun Seo, Vidya A. Chhabria, Jeff Zhang, Chaitali Chakrabarti, Ümit Y. Ogras, Yu Cao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2025

MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging.

Jinwei Tang, Jiayin Qin, Nuo Xu, Pragnya Sudershan Nalla, Yu Cao, Yang Katie Zhao, Caiwen Ding

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

CLAIRE: Composable Chiplet Libraries for AI Inference.

Pragnya Sudershan Nalla, Emad Haque, Yaotian Liu, Sachin S. Sapatnekar, Jeff Zhang, Chaitali Chakrabarti, Yu Cao

Proceedings of the Design, Automation & Test in Europe Conference, 2025

Invited: EDA for Heterogeneous Integration.

Emad Haque, Pragnya Sudershan Nalla, Chetal Choppali Sudarshan, Divya Yogi, Hangyu Zhang, Chaitali Chakrabarti, Vidya A. Chhabria, Ramesh Harjani, Jeff Zhang, Sachin S. Sapatnekar

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024

SHIFFT: A Scalable Hybrid In-Memory Computing FFT Accelerator.

Pragnya Sudershan Nalla, Zhenyu Wang, Sapan Agarwal, T. Patrick Xiao, Christopher H. Bennett, Matthew J. Marinella, Jae-sun Seo, Yu Cao

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

2023

3D-ISC: A 65nm 3D Compatible In-Sensor Computing Accelerator with Reconfigurable Tile Architecture for Real-Time DVS Data Compression.

Gokul Krishnan, Gopikrishnan Raveendran Nair, Jonghyun Oh, Anupreetham Anupreetham, Pragnya Sudershan Nalla, Ahmed Hassan, Injune Yeo, Kishore Kasichainula, Jae-sun Seo, Mingoo Seok, Yu Cao

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023