Jinyong Choi
According to our database1,
Jinyong Choi authored at least 4 papers
between 2020 and 2026.
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Bibliography
2026
A 16Gb 12.8Gb/s LPDDR6 SDRAM with 12-DQ/Sub-Channel Wide NRZ Signaling and Enhanced Reliability by Per-Row Activation Counting and Meta-Data Scheme.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
2024
6.10 A 1/1.56-inch 50Mpixel CMOS Image Sensor with 0.5μm pitch Quad Photodiode Separated by Front Deep Trench Isolation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2021
25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3<sup>rd</sup>-Generation 10nm DRAM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
5.5 A 2.1e<sup>-</sup> Temporal Noise and -105dB Parasitic Light Sensitivity Backside-Illuminated 2.3µm-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020