Jan Heisswolf

According to our database, Jan Heisswolf authored at least 23 papers between 2011 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2017

Efficient task spawning for shared memory and message passing in many-core architectures.

Aurang Zaib, Thomas Wild, Andreas Herkersdorf, Jan Heisswolf, Jürgen Becker, Andreas Weichslgartner, Jürgen Teich

J. Syst. Archit., 2017

2016

Providing fault tolerance through invasive computing.

Vahid Lari, Andreas Weichslgartner, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Jürgen Teich, Jan Heißwolf, Stephanie Friederich, Jürgen Becker

it Inf. Technol., 2016

2015

A Framework for Multi-FPGA Interconnection using Multi Gigabit Transceivers.

Michael Dreschmann, Jan Heisswolf, Michael Geiger, Manuel Haußecker, Jürgen Becker

Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

Network Interface with Task Spawning Support for NoC-Based DSM Architectures.

Aurang Zaib, Jan Heißwolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker, Andreas Herkersdorf

Proceedings of the Architecture of Computing Systems - ARCS 2015, 2015

Fault-tolerant communication in invasive networks on chip.

Jan Heisswolf, Andreas Weichslgartner, Aurang Zaib, Stephanie Friederich, Leonard Masing, Carsten Stein, Marco Duden, Roman Klopfer, Jürgen Teich, Thomas Wild, Andreas Herkersdorf, Jürgen Becker

Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

2014

A Scalable and Adaptive Network on Chip for Many-Core Architectures.

Jan Heißwolf

PhD thesis, 2014

Hardware/software debugging of large scale many-core architectures.

Stephanie Friederich, Jan Heisswolf, Jürgen Becker

Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

CAP: Communication Aware Programming.

Jan Heisswolf, Aurang Zaib, Andreas Zwinkau, Sebastian Kobbe, Andreas Weichslgartner, Jürgen Teich, Jörg Henkel, Gregor Snelting, Andreas Herkersdorf, Jürgen Becker

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure.

Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Martin Karle, Maximilian Singh, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker

Proceedings of the ARCS 2014, 2014

2013

Virtual networks - distributed communication resource management.

Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker

ACM Trans. Reconfigurable Technol. Syst., 2013

Providing multiple hard latency and throughput guarantees for packet switching networks on chip.

Jan Heisswolf, Ralf König, Martin Kupper, Jürgen Becker

Comput. Electr. Eng., 2013

NoC simulation in heterogeneous architectures for PGAS programming model.

Sascha Roloff, Andreas Weichslgartner, Jan Heißwolf, Frank Hannig, Jürgen Teich

Proceedings of the International Workshop on Software and Compilers for Embedded Systems, 2013

Efficient memory access in 2D Mesh NoC architectures using high bandwidth routers.

Jan Heisswolf, Simon Bischof, Michael Rückauer, Jürgen Becker

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

Rerouting: Scalable NoC self-optimization by distributed hardware-based connection reallocation.

Jan Heisswolf, Maximilian Singh, Martin Kupper, Ralf König, Jürgen Becker

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Hardware Supported Adaptive Data Collection for Networks on Chip.

Jan Heisswolf, Andreas Weichslgartner, Aurang Zaib, Ralf König, Thomas Wild, Andreas Herkersdorf, Jürgen Teich, Jürgen Becker

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

AUTO-GS: Self-Optimization of NoC Traffic through Hardware Managed Virtual Connections.

Aurang Zaib, Jan Heisswolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker, Andreas Herkersdorf

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Hybrid interconnect design for heterogeneous hardware accelerators.

Cuong Pham-Quoc, Jan Heisswolf, Stephan Werner, Zaid Al-Ars, Jürgen Becker, Koen Bertels

Proceedings of the Design, Automation and Test in Europe, 2013

2012

A Scalable NoC Router Design Providing QoS Support Using Weighted Round Robin Scheduling.

Jan Heisswolf, Ralf König, Jürgen Becker

Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012

Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS.

Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Invasive manycore architectures.

Jörg Henkel, Andreas Herkersdorf, Lars Bauer, Thomas Wild, Michael Hübner, Ravi Kumar Pujari, Artjom Grudnitsky, Jan Heisswolf, Aurang Zaib, Benjamin Vogel, Vahid Lari, Sebastian Kobbe

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Hardware prototyping of novel invasive multicore architectures.

Jürgen Becker, Stephanie Friederich, Jan Heisswolf, Ralf König, David May

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Architecture design space exploration of run-time scalable issue-width processors.

Ralf König, Timo Stripf, Jan Heisswolf, Jürgen Becker

Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

A Scalable Microarchitecture Design that Enables Dynamic Code Execution for Variable-Issue Clustered Processors.

Ralf König, Timo Stripf, Jan Heisswolf, Jürgen Becker

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011