Jeongho Hwang

According to our database, Jeongho Hwang authored at least 13 papers between 2009 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS.

Jeongho Hwang, Sang-Hyeok Chu, Gyu-Seob Jeong, Yeojoon Youn, Wooseok Kim, Taeik Kim, Deog-Kyoon Jeong

IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 48 Gb/s PAM-4 Transmitter With 3-Tap FFE Based on Double-Shielded Coplanar Waveguide in 65-nm CMOS.

Hyungrok Do, Jeongho Hwang, Hong-Seok Choi, Deog-Kyoon Jeong

IEEE Trans. Circuits Syst. II Express Briefs, 2020

32.4 A 0.4-to-1.2V 0.0057mm² 55fs-Transient-FoM Ring-Amplifier-Based Low-Dropout Regulator with Replica-Based PSR Enhancement.

Jun-Eun Park, Jeongho Hwang, Jonghyun Oh, Deog-Kyoon Jeong

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019

A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS.

Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang, Min-Seong Choo, Deog-Kyoon Jeong

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS.

Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Gyu-Seob Jeong, Daehyun Koh, Kwanseo Park, Sungwoo Kim, Deog-Kyoon Jeong

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

56Gb/s PAM-4 VCSEL Transmitter with Quarter-Rate Forwarded Clock using 65nm CMOS Circuits.

Jeongho Hwang, Hyungrok Do, Hong-Seok Choi, Gyu-Seob Jeong, Daehyun Koh, Sungwoo Kim, Deog-Kyoon Jeong

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019

2018

25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections.

Gyu-Seob Jeong, Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Daehyun Koh, Daeyoung Yun, Jinhyung Lee, Kwanseo Park, Han-Gon Ko, Kwangho Lee, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong

IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 32 Gb/s, 201 mW, MZM/EAM Cascode Push-Pull CML Driver in 65 nm CMOS.

Jeongho Hwang, Gyu-Seob Jeong, Woo-Rham Bae, Jun-Eun Park, Chang-Soo Yoon, Jungmin Yoon, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong

IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 35-Gb/s 0.65-pJ/b Asymmetric Push-Pull Inverter-Based VCSEL Driver With Series Inductive Peaking in 65-nm CMOS.

Hong-Seok Choi, Jeongho Hwang, Gyu-Seob Jeong, Gyungock Kim, Deog-Kyoon Jeong

IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS.

Kwanseo Park, Woo-Rham Bae, Jinhyung Lee, Jeongho Hwang, Deog-Kyoon Jeong

IEEE J. Solid State Circuits, 2018

4-Channel Push-Pull VCSEL Drivers for HDMI Active Optical Cable in 0.18-μm CMOS.

Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Gyu-Seob Jeong, Daehyun Koh, Seong Ho Park, Deog-Kyoon Jeong

Proceedings of the International Symposium on Low Power Electronics and Design, 2018

2011

Blockwise Amplify-and-Forward Relaying Strategies for Multipoint-to-Multipoint MIMO Networks.

Jaesin Kim, Jeongho Hwang, Kyoung-Jae Lee, Inkyu Lee

IEEE Trans. Wirel. Commun., 2011

2009

Block diagonalization approach for amplify-and-forward relay systems in MIMO multi-user channels.

Jeongho Hwang, Kyoung-Jae Lee, Hakjea Sung, Inkyu Lee

Proceedings of the IEEE 20th International Symposium on Personal, 2009