Jeongho Hwang

Orcid: 0000-0003-2989-782X

According to our database1, Jeongho Hwang authored at least 17 papers between 2009 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS.
IEEE J. Solid State Circuits, 2021

A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS.
IEEE Access, 2021

2020
A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 48 Gb/s PAM-4 Transmitter With 3-Tap FFE Based on Double-Shielded Coplanar Waveguide in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

32.4 A 0.4-to-1.2V 0.0057mm<sup>2</sup> 55fs-Transient-FoM Ring-Amplifier-Based Low-Dropout Regulator with Replica-Based PSR Enhancement.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Optical Receiver Front-end for Active Optical Cable in 180 nm CMOS.
Proceedings of the International SoC Design Conference, 2020

2019
A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

56Gb/s PAM-4 VCSEL Transmitter with Quarter-Rate Forwarded Clock using 65nm CMOS Circuits.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019

2018
25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 32 Gb/s, 201 mW, MZM/EAM Cascode Push-Pull CML Driver in 65 nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 35-Gb/s 0.65-pJ/b Asymmetric Push-Pull Inverter-Based VCSEL Driver With Series Inductive Peaking in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS.
IEEE J. Solid State Circuits, 2018

4-Channel Push-Pull VCSEL Drivers for HDMI Active Optical Cable in 0.18-μm CMOS.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS.
Proceedings of the 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2018

2011
Blockwise Amplify-and-Forward Relaying Strategies for Multipoint-to-Multipoint MIMO Networks.
IEEE Trans. Wirel. Commun., 2011

2009
Block diagonalization approach for amplify-and-forward relay systems in MIMO multi-user channels.
Proceedings of the IEEE 20th International Symposium on Personal, 2009


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