John S. Brunhaver

Orcid: 0000-0002-0156-9392

According to our database1, John S. Brunhaver authored at least 13 papers between 2010 and 2024.

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Bibliography

2024
Cyclebite: Extracting Task Graphs From Unstructured Compute-Programs.
IEEE Trans. Computers, January, 2024

2023
Efficient Error Detection for Matrix Multiplication With Systolic Arrays on FPGAs.
IEEE Trans. Computers, August, 2023

2022
Profile-Guided Parallel Task Extraction and Execution for Domain Specific Heterogeneous SoC.
Proceedings of the IEEE Intl Conf on Parallel & Distributed Processing with Applications, 2022

Self-correcting Flip-flops for Triple Modular Redundant Logic in a 12-nm Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022


2020
Automated Parallel Kernel Extraction from Dynamic Application Traces.
CoRR, 2020

2019
Physically Unclonable Functions Using Foundry SRAM Cells.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Itemization and Track Limitations of Fan-Out-Free Functions for Static CMOS Functional Cells.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

2015
Building Conflict-Free FFT Schedules.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2014
Darkroom: compiling high-level image processing code into hardware pipelines.
ACM Trans. Graph., 2014

2013
FPU Generator for Design Space Exploration.
Proceedings of the 21st IEEE Symposium on Computer Arithmetic, 2013

2012
Avoiding game over: bringing design to the next level.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2010
Hardware implementation of micropolygon rasterization with motion and defocus blur.
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Conference on High Performance Graphics 2010, 2010


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