Shail Dave

Orcid: 0000-0003-4262-3938

According to our database1, Shail Dave authored at least 11 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2024
Cyclebite: Extracting Task Graphs From Unstructured Compute-Programs.
IEEE Trans. Computers, January, 2024

2023
Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Explainable-DSE: An Agile and Explainable Exploration of Efficient HW/SW Codesigns of Deep Learning Accelerators Using Bottleneck Analysis.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022
Special Session: Towards an Agile Design Methodology for Efficient, Reliable, and Secure ML Systems.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

2021
SPX64: A Scratchpad Memory for General-purpose Microprocessors.
ACM Trans. Archit. Code Optim., 2021

Hardware Acceleration of Sparse and Irregular Tensor Computations of ML Models: A Survey and Insights.
Proc. IEEE, 2021

2020
dMazeRunner: Optimizing Convolutions on Dataflow Accelerators.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

2019
dMazeRunner: Executing Perfectly Nested Loops on Dataflow Accelerators.
ACM Trans. Embed. Comput. Syst., 2019

2018
URECA: Unified register file for CGRAs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

LASER: A hardware/software approach to accelerate complicated loops on CGRAs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

RAMP: resource-aware mapping for CGRAs.
Proceedings of the 55th Annual Design Automation Conference, 2018


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