K. Banerjee

According to our database1, K. Banerjee authored at least 8 papers between 1988 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
Towards low damage and fab-compatible top-contacts in MX2 transistors using a combined synchronous pulse atomic layer etch and wet-chemical etch approach.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022
A comprehensive variability study of doped HfO2 FeFET for memory applications.
Proceedings of the IEEE International Memory Workshop, 2022

At the Extreme of 3D-NAND Scaling: 25 nm Z-Pitch with 10 nm Word Line Cells.
Proceedings of the IEEE International Memory Workshop, 2022

High-K incorporated in a SiON tunnel layer for 3D NAND programming voltage reduction.
Proceedings of the IEEE International Memory Workshop, 2022

Device engineering guidelines for performance boost in IGZO front gated TFTs based on defect control.
Proceedings of the International Conference on IC Design and Technology, 2022

2021
First demonstration of ferroelectric Si: HfO2 based 3D FE-FET with trench architecture for dense nonvolatile memory application.
Proceedings of the IEEE International Memory Workshop, 2021

2005
Determination of EOQ of Multi-Item inventory Problems through nonlinear Goal Programming with penalty Function.
Asia Pac. J. Oper. Res., 2005

1988
An SIMD machine for low-level vision.
Inf. Sci., 1988


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