Devin Verreck

According to our database1, Devin Verreck authored at least 10 papers between 2016 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
The Promise of 2-D Materials for Scaled Digital and Analog Applications.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

Impact of gate stack processing on the hysteresis of 300 mm integrated WS2 FETs.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

Enabling 3D NAND Trench Cells for Scaled Flash Memories.
Proceedings of the IEEE International Memory Workshop, 2023

2022

At the Extreme of 3D-NAND Scaling: 25 nm Z-Pitch with 10 nm Word Line Cells.
Proceedings of the IEEE International Memory Workshop, 2022

Analysis of BTI in 300 mm integrated dual-gate WS2 FETs.
Proceedings of the Device Research Conference, 2022

2021
A TCAD Compatible SONOS Trapping Layer Model for Accurate Programming Dynamics.
Proceedings of the IEEE International Memory Workshop, 2021

2019
Impact of Mechanical Stress on the Electrical Performance of 3D NAND.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

2016

Non-uniform strain in lattice-mismatched heterostructure tunnel field-effect transistors.
Proceedings of the 46th European Solid-State Device Research Conference, 2016


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