Jan Van Houdt

According to our database1, Jan Van Houdt authored at least 31 papers between 1998 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2014, "For contributions to flash memory devices".

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2023
Evaluating the Effects of FeFET Device Variability on Charge Sharing Based AiMC Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Improved MW of IGZO-channel FeFET by Reading Scheme Optimization and Interfacial Engineering.
Proceedings of the IEEE International Memory Workshop, 2023

Optimization of Retention in Ferroelectricity Boosted Gate Stacks for 3D NAND.
Proceedings of the IEEE International Memory Workshop, 2023

Understanding the impact of La dopant position on the ferroelectric properties of hafnium zirconate.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022
Enhanced performance and low-power capability of SiGeAsSe-GeSbTe 1S1R phase-change memory operated in bipolar mode.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Insight to Data Retention loss in ferroelectric Hf0.5Zr0.5O2 pFET and nFET from simultaneous PV and IV measurements.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Trap-polarization interaction during low-field trap characterization on hafnia-based ferroelectric gatestacks.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

Degradation mechanism of amorphous IGZO-based bipolar metal-semiconductor-metal selectors.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

Modelling ultra-fast threshold voltage instabilities in Hf-based ferroelectrics.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

A comprehensive variability study of doped HfO2 FeFET for memory applications.
Proceedings of the IEEE International Memory Workshop, 2022

2021
Analog In-memory Computing in FeFET-based 1T1R Array for Edge AI Applications.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

Impact of mechanical strain on wakeup of HfO2 ferroelectric memory.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

Threshold switching in a-Si and a-Ge based MSM selectors and its implications for device reliability.
Proceedings of the IEEE International Memory Workshop, 2021

Understanding the memory window in 1T-FeFET memories: a depolarization field perspective.
Proceedings of the IEEE International Memory Workshop, 2021

First demonstration of ferroelectric Si: HfO2 based 3D FE-FET with trench architecture for dense nonvolatile memory application.
Proceedings of the IEEE International Memory Workshop, 2021

2020
Impact of Ferroelectric Wakeup on Reliability of Laminate based Si-doped Hafnium Oxide (HSO) FeFET Memory Cells.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019
Gate Stack Optimization Toward Disturb-Free Operation of Ferroelectric HSO based FeFET for NAND Applications.
Proceedings of the 19th Non-Volatile Memory Technology Symposium, 2019

New Insights into the Imprint Effect in FE-HfO2 and its Recovery.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

2018
Investigation of the endurance of FE-HfO2 devices by means of TDDB studies.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

2017
From planar to vertical capacitors: A step towards ferroelectric V-FeFET integration.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

Doped GeSe materials for selector applications.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

2014
Optimization of inter-gate-dielectrics in hybrid float gate devices to reduce window instability during memory operations.
Microelectron. Reliab., 2014

Assessment methodology of the lateral migration component in data retention of 3D SONOS memories.
Microelectron. Reliab., 2014

2012
Trades-off between lithography line edge roughness and error-correcting codes requirements for NAND Flash memories.
Microelectron. Reliab., 2012

2011
Cross-cell interference variability aware model of fully planar NAND Flash memory including line edge roughness.
Microelectron. Reliab., 2011

2007
Characterization of charge trapping in SiO<sub>2</sub>/Al<sub>2</sub>O<sub>3</sub> dielectric stacks by pulsed C-V technique.
Microelectron. Reliab., 2007

Distribution and generation of traps in SiO<sub>2</sub>/Al<sub>2</sub>O<sub>3</sub> gate stacks.
Microelectron. Reliab., 2007

2003
The HIMOS flash technology: the alternative solution for low-cost embedded memory.
Proc. IEEE, 2003

2001
Simulation of 0.35 μm/0.25 μm CMOS Technology Doping Profiles.
VLSI Design, 2001

A flash memory technology with quasi-virtual ground array for low-cost embedded applications.
IEEE J. Solid State Circuits, 2001

1998
Novel level-identifying circuit for flash multilevel memories.
IEEE J. Solid State Circuits, 1998


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