Quentin Smets

According to our database1, Quentin Smets authored at least 10 papers between 2016 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Towards low damage and fab-compatible top-contacts in MX2 transistors using a combined synchronous pulse atomic layer etch and wet-chemical etch approach.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Integration of epitaxial monolayer MX₂ channels on 300mm wafers via Collective-Die-To-Wafer (CoD2W) transfer.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

The Promise of 2-D Materials for Scaled Digital and Analog Applications.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

Impact of gate stack processing on the hysteresis of 300 mm integrated WS2 FETs.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

2022
Analysis of BTI in 300 mm integrated dual-gate WS2 FETs.
Proceedings of the Device Research Conference, 2022

2019
Experimental calibration of the temperature dependence of the heterojunction bandgap in III-V tunneling devices.
Proceedings of the Device Research Conference, 2019

Tunnel FETs using Phosphorene/ReS2 heterostructures.
Proceedings of the Device Research Conference, 2019

2017
WS2 transistors on 300 mm wafers with BEOL compatibility.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

Tunneling transistors based on MoS2/MoTe2 Van der Waals heterostructures.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

2016


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