Kedar Janardan Dhori

According to our database, Kedar Janardan Dhori authored at least 11 papers between 2014 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Retention Problem Free High Density 4T SRAM cell with Adaptive Body Bias in 18nm FD-SOI.

Chandan Kumar, Rahul Kumar, Anuj Grover, Shouri Chatterjee, Kedar Janardan Dhori, Harsh Rawat

Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

40nm Ultra-low Leakage SRAM with Embedded Sub-threshold Analog Closed Loop System for Efficient Source Biasing of the Memory Array in Retention Mode.

Kedar Janardan Dhori, Promod Kumar, Christophe Lecocq, Pascal Urard, Olivier Callen, Florian Cacho, Maryline Parra, Prashant Pandey, Daniel Noblet

Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

3-Stage Pipelined Hierarchical SRAMs with Burst Mode Read in 65nm LSTP CMOS.

Mukesh Kumar Srivastav, Rimjhim, Roshan Mishra, Anuj Grover, Kedar Janardan Dhori, Harsh Rawat

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

Charge Scavenging Gate Coupled Hierarchical Bitline Scheme for Ultra-Low Power SRAMs in 65nm LSTP CMOS.

Mukesh Kumar Srivastav, Rimjhim, Govind Soni, Umang Mittal, Rupali Tewari, Riya Yadav, Anuj Grover, Kedar Janardan Dhori, Harsh Rawat

Proceedings of the 28th IEEE International Conference on Electronics, 2021

Circuit Monitoring Across Design Life-Cycle in 28nm FD-SOI and 40nm Bulk CMOS technologies.

Sylvain Clerc, Kedar Janardan Dhori, Robin M. Wilson, Rohit Goel, Sébastien Marchal, Franck Pourchon, Christian Dutto, Ricardo Gomez Gomez

Proceedings of the 47th ESSCIRC 2021, 2021

2020

Diagnostic Circuit for Latent Fault Detection in SRAM Row Decoder.

Shivendra Singh, Varshita Gupta, Anuj Grover, Kedar Janardan Dhori

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

2017

High-yield design of high-density SRAM for low-voltage and low-leakage operations.

Kedar Janardan Dhori, Hitesh Chawla, Ashish Kumar, Prashant Pandey, Promod Kumar, Lorenzo Ciampolini, Florian Cacho, Damien Croain

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016

Temperature-based adaptive memory sub-system in 28nm UTBB FDSOI.

Amit Chhabra, Mudit Srivastava, Prakhar Raj Gupta, Kedar Janardan Dhori, Philippe Triolet, Thierry Di Gilio, Nitin Bansal, B. Sujatha

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

A CMOS 90nm 50Mhz Supply Noise Tolerant High Density 8T-NAND ROM.

Kedar Janardan Dhori, Vinay Kumar, Ashish Kumar

Proceedings of the 28th International Conference on VLSI Design, 2015

A 6T-SRAM in 28nm FDSOI technology with Vmin of 0.52V using assisted read and write operation.

Ashish Kumar, Vinay Kumar, Dhori Kedar Janardan, G. S. Visweswaran, Kaushik Saha

Proceedings of the 2015 International Conference on IC Design & Technology, 2015

2014

Write Assist Circuit to Cater Reliability and Floating Bit Line Problem of Negative Bit Line Assist Technique for Single or Multiport Static Random Access Memory.

Kedar Janardan Dhori, Vinay Kumar, Harsh Rawat

IEEE Trans. Very Large Scale Integr. Syst., 2014