Damien Croain

According to our database1, Damien Croain authored at least 7 papers between 2011 and 2017.

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Bibliography

2017
High-yield design of high-density SRAM for low-voltage and low-leakage operations.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016
28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A 28nm FD-SOI standard cell 0.6-1.2V open-loop frequency multiplier for low power SoC clocking.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors.
Proceedings of the ESSCIRC Conference 2015, 2015

2011
Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Bottom-up digital system-level reliability modeling.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011


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