Damien Croain

According to our database, Damien Croain authored at least 7 papers between 2011 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2017

High-yield design of high-density SRAM for low-voltage and low-leakage operations.

Kedar Janardan Dhori, Hitesh Chawla, Ashish Kumar, Prashant Pandey, Promod Kumar, Lorenzo Ciampolini, Florian Cacho, Damien Croain

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016

28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications.

Rossella Ranica, Nicolas Planes, Vincent Huard, Olivier Weber, Daniel Noblet, Damien Croain, Fabien Giner, Sylvie Naudet, P. Mergault, S. Ibars, A. Villaret, Maryline Parra, Sébastien Haendler, M. Quoirin, Florian Cacho, C. Julien, F. Terrier, Lorenzo Ciampolini, David Turgis, Christophe Lecocq, Franck Arnaud

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A 28nm FD-SOI standard cell 0.6-1.2V open-loop frequency multiplier for low power SoC clocking.

Martin Cochet, Sylvain Clerc, Mehdi Naceur, Pierre Schamberger, Damien Croain, Jean-Luc Autran, Philippe Roche

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing.

Sylvain Clerc, Mehdi Saligane, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Cyril Bottoni, David Bol, Julien De Vos, Dominique Zamora, Benjamin Coeffic, Dimitri Soussan, Damien Croain, Mehdi Naceur, Pierre Schamberger, Philippe Roche, Dennis Sylvester

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors.

Fady Abouzeid, Sylvain Clerc, Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Damien Croain, Gilles Gasiot, Dimitri Soussan, Philippe Roche

Proceedings of the ESSCIRC Conference 2015, 2015

2011

Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec.

Julien Le Coz, Philippe Flatresse, Sylvain Engels, Alexandre Valentian, Marc Belleville, Christine Raynaud, Damien Croain, Pascal Urard

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Bottom-up digital system-level reliability modeling.

N. Ruiz Amador, Vincent Huard, E. Pion, Florian Cacho, Damien Croain, V. Robert, Sylvain Engels, Philippe Flatresse, Lorena Anghel

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011