Lorenzo Ciampolini

According to our database1, Lorenzo Ciampolini authored at least 14 papers between 2012 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


A Near-Instantaneous and Non-Invasive Erasure Design Technique to Protect Sensitive Data Stored in Secure SRAMs.
Proceedings of the 47th ESSCIRC 2021, 2021

Storage Class Memory with Computing Row Buffer: A Design Space Exploration.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

A 128 kb 7T SRAM Using a Single-Cycle Boosting Mechanism in 28-nm FD-SOI.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

High-yield design of high-density SRAM for low-voltage and low-leakage operations.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

RAPIDO Testing and Modeling of Assisted Write and Read Operations for SRAMs.
Proceedings of the 25th IEEE North Atlantic Test Workshop, 2016

Efficient yield estimation through generalized importance sampling with application to NBL-assisted SRAM bitcells.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI.
IEEE J. Solid State Circuits, 2014

Impact of Random Telegraph Signals on 6T high-density SRAM in 28nm UTBB FD-SOI.
Proceedings of the 44th European Solid State Device Research Conference, 2014

Multiple-pulse dynamic stability and failure analysis of low-voltage 6T-SRAM bitcells in 28nm UTBB-FDSOI.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI.
Proceedings of the ESSCIRC 2013, 2013

Proposal of a new ultra low leakage 10T sub threshold SRAM bitcell.
Proceedings of the International SoC Design Conference, 2012