Robin Wilson

According to our database1, Robin Wilson authored at least 27 papers between 2003 and 2018.

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Timeline

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Bibliography

2018
A 6-Wire Plug and Play Clockless Distributed On-Chip-Sensor Network in 28 nm UTBB FD-SOI.
J. Low Power Electronics, 2018

2017
Introducing Turing's mathematics.
Proceedings of the Turing Guide., 2017

2015
A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking.
J. Solid-State Circuits, 2015

Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2014
A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC.
J. Solid-State Circuits, 2014

A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization.
J. Solid-State Circuits, 2014

Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI.
J. Solid-State Circuits, 2014

Clockless Design Performance Monitoring for Nanometer Technologies.
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

2013
Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013


2010
On-Chip Process Variability Monitoring Flow.
J. Low Power Electronics, 2010

2009
Timing margin evaluation with a simple statistical timing analysis flow.
J. Embedded Computing, 2009

Product On-Chip Process Compensation for Low Power and Yield Enhancement.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

2007
Temperature- and Voltage-Aware Timing Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Temperature and voltage aware timing analysis: application to voltage drops.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Logical effort model extension to propagation delay representation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects.
Integr., 2006

Design for Volume Manufacturing in the Deep Submicron ERA.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Statistical Characterization of Library Timing Performance.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Yield Enhancement Methodology for CMOS Standard Cells.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Timing analysis in presence of supply voltage and temperature variations.
Proceedings of the 2006 International Symposium on Physical Design, 2006

2005
An Open Platform for Developing Multiprocessor SoCs.
IEEE Computer, 2005

Temperature Dependency in UDSM Process.
Proceedings of the Integrated Circuit and System Design, 2005

2004
Physical Extension of the Logical Effort Model.
Proceedings of the Integrated Circuit and System Design, 2004

Temperature Dependence in Low Power CMOS UDSM Process.
Proceedings of the Integrated Circuit and System Design, 2004

2003
Information Management and Interoperability Strategies: The Case for Digital Identifiers.
Proceedings of the IADIS International Conference WWW/Internet 2003, 2003


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