Kumiko Nomura

According to our database, Kumiko Nomura authored at least 20 papers between 2001 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Synchronized Stepwise Control of Firing and Learning Thresholds in a Spiking Randomly Connected Neural Network toward Hardware Implementation.

Kumiko Nomura, Yoshifumi Nishi

CoRR, 2024

2020

Dynamic Firing on Static Analog/Digital Neuron Circuits with Resistive Synapses for Time-Series Neural Network.

Takao Marukame, Junichi Sugino, Toshimitsu Kitamura, Kazuo Ishikawa, Koji Takahashi, Yutaka Tamura, Kumiko Nomura, Koichi Mizushima, Yoshifumi Nishi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Nonlinear Operation of Static-Binary Neuron Circuits and Dynamic Memristive Devices for STDP Learning.

Takao Marukame, Junichi Sugino, Toshimitsu Kitamura, Kazuo Ishikawa, Koji Takahashi, Yutaka Tamura, Radu Berdan, Kumiko Nomura, Yoshifumi Nishi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

Proposal, analysis and demonstration of Analog/Digital-mixed Neural Networks based on memristive device arrays.

Takao Marukame, Kumiko Nomura, Mari Matusmoto, Satoshi Takaya, Yoshifumi Nishi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Novel memory hierarchy with e-STT-MRAM for near-future applications.

Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe

Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

2014

Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures.

Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Novel nonvolatile memory hierarchies to realize "normally-off mobile processors".

Shinobu Fujita, Kumiko Nomura, Hiroki Noguchi, Susumu Takeda, Keiko Abe

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory.

Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Designing Nonvolatile Reconfigurable Switch-based FPGA through Overall Circuit Performance Evaluation.

Kazutaka Ikegami, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Masato Oda, Shinobu Fujita

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

2010

Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies.

Kumiko Nomura, Keiko Abe, Shinobu Fujita, Yasuhiko Kurosawa, Atsushi Kageshima

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

Perspectives and Issues in 3D-IC from Designers' Point of View.

Shinobu Fujita, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Tetsufumi Tanamoto

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

On the three-dimensional orthogonal drawing of series-parallel graphs (extended abstract).

Satoshi Tayu, Kumiko Nomura, Shuichi Ueno

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

3-D Nanoarchitectures With Carbon Nanotube Mechanical Switches for Future On-Chip Network Beyond CMOS Architecture.

Shinobu Fujita, Kumiko Nomura, Keiko Abe, Thomas H. Lee

IEEE Trans. Circuits Syst. I Regul. Pap., 2007

2006

Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices.

Kumiko Nomura, Keiko Abe, Shinobu Fujita, André DeHon

Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

3D on-chip networking technology based on post-silicon devices for future networks-on-chip.

Shinobu Fujita, Kumiko Nomura, Keiko Abe, Thomas H. Lee

Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

On the two-dimensional orthogonal drawing of series-parallel graphs.

Satoshi Tayu, Kumiko Nomura, Shuichi Ueno

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2004

Sparse networks tolerating random faults.

Toshinori Yamada, Kumiko Nomura, Shuichi Ueno

Discret. Appl. Math., 2004

On the Orthogonal Drawing of Outerplanar Graphs.

Kumiko Nomura, Satoshi Tayu, Shuichi Ueno

Proceedings of the Computing and Combinatorics, 10th Annual International Conference, 2004

2003

Optimal adaptive parallel diagnosis for arrays.

Toshinori Yamada, Kumiko Nomura, Shuichi Ueno

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2001

On Adaptive Fault Diagnosis for Multiprocessor Systems.

Kumiko Nomura, Toshinori Yamada, Shuichi Ueno

Proceedings of the Algorithms and Computation, 12th International Symposium, 2001