Laura Pozzi
Orcid: 0000-0003-1083-8782Affiliations:
- University of Lugano, Switzerland
According to our database1,
Laura Pozzi
authored at least 74 papers
between 1997 and 2024.
Collaborative distances:
Collaborative distances:
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Online presence:
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on orcid.org
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on inf.unisi.ch
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on usi.to
On csauthors.net:
Bibliography
2024
Empir. Softw. Eng., April, 2024
2023
ACM Trans. Design Autom. Electr. Syst., March, 2023
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023
SAT-MapIt: A SAT-based Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
SAT-MapIt: An Open Source Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures.
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023
ErrorEval: an Open-Source Worst-Case-Error Evaluation Framework for Approximate Computing.
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
INCLASS: Incremental Classification Strategy for Self-Aware Epileptic Seizure Detection.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
IEEE Trans. Emerg. Top. Comput., 2021
Guest Editorial: IEEE TC Special Section on Compiler Optimizations for FPGA-Based Systems.
IEEE Trans. Computers, 2021
IEEE Embed. Syst. Lett., 2021
CoRR, 2021
2020
Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Judiciously Spreading Approximation Among Arithmetic Components with Top-Down Inexact Hardware Design.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020
2019
RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source Code.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-Signal Processing.
IEEE Embed. Syst. Lett., 2019
Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Partition and Propagate: an Error Derivation Algorithm for the Design of Approximate Circuits.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Heterogeneous and Inexact: Maximizing Power Efficiency of Edge Computing Sensors for Health Monitoring Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Machine Learning Approach for Loop Unrolling Factor Prediction in High Level Synthesis.
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
A partitioning strategy for exploring error-resilience in circuits: work-in-progress.
Proceedings of the International Conference on Compilers, 2018
2017
An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery.
ACM Trans. Embed. Comput. Syst., 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
2016
IET Comput. Digit. Tech., 2016
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
2015
Maximum Convex Subgraphs Under I/O Constraint for Automatic Identification of Custom Instructions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
2013
An Effective Exact Algorithm and a New Upper Bound for the Number of Contacts in the Hydrophobic-Polar Two-Dimensional Lattice Model.
J. Comput. Biol., 2013
2012
Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2009
Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology.
Trans. Comput. Sci., 2009
Guest Editorial Special Section on the IEEE Symposium on Application Specific Processors 2008.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration.
Proceedings of the Design, Automation and Test in Europe, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
Proceedings of the IEEE Symposium on Application Specific Processors, 2008
Proceedings of the 2008 International Conference on Compilers, 2008
2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007
Proceedings of the Embedded Computer Systems: Architectures, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors.
IEEE Trans. Very Large Scale Integr. Syst., 2006
Exact and approximate algorithms for the extension of embedded processor instruction sets.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Microprocess. Microsystems, 2006
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Automatic identification of application-specific functional units with architecturally visible storage.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 2006 International Conference on Compilers, 2006
2005
IEEE Des. Test Comput., 2005
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement.
Proceedings of the 2005 Design, 2005
Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
Exploiting pipelining to relax register-file port constraints of instruction-set extensions.
Proceedings of the 2005 International Conference on Compilers, 2005
2004
Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units.
Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004
Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors.
Proceedings of the Field Programmable Logic and Application, 2004
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004
Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors.
Proceedings of the 2004 Design, 2004
Proceedings of the 41th Design Automation Conference, 2004
Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004
2003
Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints.
Int. J. Parallel Program., 2003
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003
2002
Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors.
Proceedings of the 2002 Design, 2002
2001
Determining the Optimum Extended Instruction-Set Architecture for Application Specific Reconfigurable VLIW CPUs.
Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001
2000
Determining the optimum extended instruction-set architecture for application specific reconfigurable VLIW CPUs (poster abstract).
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000
1999
Proceedings of the 1999 Design, 1999
1998
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998
1997
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997