Zeynep Toprak Deniz

According to our database1, Zeynep Toprak Deniz authored at least 26 papers between 2003 and 2020.

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Bibliography

2020
Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS.
IEEE J. Solid State Circuits, 2020

Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS".
IEEE J. Solid State Circuits, 2020

A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS.
IEEE J. Solid State Circuits, 2020

2019
A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14nm SOI CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS.
IEEE J. Solid State Circuits, 2018

2016
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.
IEEE J. Solid State Circuits, 2016

3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.
IEEE J. Solid State Circuits, 2015

IBM POWER8 circuit design and energy optimization.
IBM J. Res. Dev., 2015

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
5.1 POWER8<sup>TM</sup>: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8<sup>TM</sup> microprocessor.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

The POWER8<sup>TM</sup> processor: Designed for big data, analytics, and cloud environments.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

2012
Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage.
IEEE J. Solid State Circuits, 2012

Root cause identification of an hard-to-find on-chip power supply coupling fail.
Proceedings of the 2012 IEEE International Test Conference, 2012

A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2009
Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology.
Trans. Comput. Sci., 2009

Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18μm CMOS technology.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation.
IEEE J. Solid State Circuits, 2007

A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

2006
Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

2005
Low-power current mode logic for improved DPA-resistance in embedded systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003
Design and realization of a modular 200 MSample/s 12-bit pipelined A/D converter block using deep-submicron digital CMOS technology.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003


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