Zeynep Toprak Deniz
Orcid: 0000-0003-2588-6912
According to our database1,
Zeynep Toprak Deniz
authored at least 30 papers
between 2003 and 2023.
Collaborative distances:
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Bibliography
2023
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links.
IEEE J. Solid State Circuits, 2023
2022
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS.
IEEE J. Solid State Circuits, 2020
Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS".
IEEE J. Solid State Circuits, 2020
IEEE J. Solid State Circuits, 2020
2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14nm SOI CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
IEEE J. Solid State Circuits, 2018
2016
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.
IEEE J. Solid State Circuits, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.
IEEE J. Solid State Circuits, 2015
A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
5.1 POWER8<sup>TM</sup>: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8<sup>TM</sup> microprocessor.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
The POWER8<sup>TM</sup> processor: Designed for big data, analytics, and cloud environments.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014
2012
Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage.
IEEE J. Solid State Circuits, 2012
Proceedings of the 2012 IEEE International Test Conference, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2009
Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology.
Trans. Comput. Sci., 2009
Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation.
IEEE J. Solid State Circuits, 2007
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007
2006
Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2003
Design and realization of a modular 200 MSample/s 12-bit pipelined A/D converter block using deep-submicron digital CMOS technology.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003