Vianney Lapotre
Orcid: 0000-0002-8091-0703
According to our database1,
Vianney Lapotre
authored at least 44 papers
between 2012 and 2023.
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Bibliography
2023
On The Effect of Replacement Policies on The Security of Randomized Cache Architectures.
CoRR, 2023
Work in Progress: Thwarting Timing Attacks in Microcontrollers using Fine-grained Hardware Protections.
Proceedings of the IEEE European Symposium on Security and Privacy, 2023
Contributions à la sécurité des systèmes embarqués face aux attaques logiques et physiques. (Contributions to the security of embedded systems against logical and physical attacks).
, 2023
2022
The Kingsguard OS-level mitigation against cache side-channel attacks using runtime detection.
Ann. des Télécommunications, 2022
Processor Extensions for Hardware Instruction Replay against Fault Injection Attacks.
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022
2020
FLUSH + PREFETCH: A countermeasure against access-driven cache-based side-channel attacks.
J. Syst. Archit., 2020
J. Inf. Secur. Appl., 2020
Winter is here! A decade of cache-based side-channel attacks, detection & mitigation for RSA.
Inf. Syst., 2020
Meet the Sherlock Holmes' of Side Channel Leakage: A Survey of Cache SCA Detection Techniques.
IEEE Access, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
Proceedings of the 7th IEEE Conference on Communications and Network Security, 2019
2018
ACM Trans. Embed. Comput. Syst., 2018
Hardware/Software Co-Design of an Accelerator for FV Homomorphic Encryption Scheme Using Karatsuba Algorithm.
IEEE Trans. Computers, 2018
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018
Proceedings of the 9th IFIP International Conference on New Technologies, 2018
NIGHTs-WATCH: a cache-based side-channel intrusion detector using hardware performance counters.
Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, 2018
Machine Learning For Security: The Case of Side-Channel Attack Detection at Run-time.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Proceedings of the 2018 Global Information Infrastructure and Networking Symposium, 2018
A novel lightweight hardware-assisted static instrumentation approach for ARM SoC using debug components.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018
2017
ACM Trans. Embed. Comput. Syst., 2017
Dynamic configuration management of a multi-standard and multi-mode reconfigurable multi-ASIP architecture for turbo decoding.
EURASIP J. Adv. Signal Process., 2017
Proceedings of the 14th International Joint Conference on e-Business and Telecommunications (ICETE 2017), 2017
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Proceedings of the Codes, Cryptology and Information Security, 2017
2016
A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding.
IEEE Trans. Very Large Scale Integr. Syst., 2016
MPSoCSim extension: An OVP simulator for the evaluation of cluster-based multi and many-core architectures.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016
ALMOS Many-Core Operating System Extension with New Secure-Enable Mechanisms for Dynamic Creation of Secure Zones.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016
Fast polynomial arithmetic for Somewhat Homomorphic Encryption operations in hardware with Karatsuba algorithm.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
2015
Exploration of polynomial multiplication algorithms for homomorphic encryption schemes.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
Performance exploration of partially connected 3D NoCs under manufacturing variability.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
2013
Tech. Sci. Informatiques, 2013
Rapid design and prototyping of a reconfigurable decoder architecture for QC-LDPC codes.
Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013
An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013
A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
2012
An analytical approach for sizing of heterogeneous multiprocessor flexible platforms for iterative demapping and channel decoding.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012