Mohammad Saber Golanbari

According to our database1, Mohammad Saber Golanbari authored at least 25 papers between 2015 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
Achieving Energy Efficiency for Near-Threshold Circuits Through Postfabrication Calibration and Adaptation.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Bayesian Optimized Mixture Importance Sampling for High-Sigma Failure Rate Estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Selective Flip-Flop Optimization for Reliable Digital Circuit Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019
Bayesian Optimized Importance Sampling for High Sigma Failure Rate Estimation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Inkjet-Printed EGFET-Based Physical Unclonable Function - Design, Evaluation, and Fabrication.
IEEE Trans. Very Large Scale Integr. Syst., 2018

VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Optimizing Datapaths for Near Threshold Computing.
Proceedings of the 15th International Conference on Synthesis, 2018

Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications.
Proceedings of the IEEE International Test Conference, 2018

Reliable memory PUF design for low-power applications.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Design and evaluation of physical unclonable function for inorganic printed electronics.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Runtime adjustment of IoT system-on-chips for minimum energy operation.
Proceedings of the 55th Annual Design Automation Conference, 2018

Balancing resiliency and energy efficiency of functional units in ultra-low power systems.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Temperature-Aware Dynamic Voltage Scaling to Improve Energy Efficiency of Near-Threshold Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Post-fabrication calibration of Near-Threshold circuits for energy efficiency.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Design flows for resilient energy-efficient systems.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Aging-aware coding scheme for memory arrays.
Proceedings of the 22nd IEEE European Test Symposium, 2017

VAET-STT: A variation aware estimator tool for STT-MRAM based memories.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Leveraging aging effect to improve SRAM-based true random number generators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Hold-time violation analysis and fixing in near-threshold region.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Maximizing Energy Efficiency in NTC by Variation-Aware Microprocessor Pipeline Optimization.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

A cross-layer approach for resiliency and energy efficiency in near threshold computing.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Variation-aware near threshold circuit synthesis.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Fault injection acceleration by simultaneous injection of non-interacting faults.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Analysis and optimization of flip-flops under process and runtime variations.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Aging guardband reduction through selective flip-flop optimization.
Proceedings of the 20th IEEE European Test Symposium, 2015


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