Anteneh Gebregiorgis

Orcid: 0000-0001-5909-4927

Affiliations:
  • Delft University of Technology, Department of Quantum and Computer Engineering, The Netherlands
  • Karlsruhe Institute of Technology, ITEC, Germany


According to our database1, Anteneh Gebregiorgis authored at least 49 papers between 2015 and 2023.

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Bibliography

2023
A Survey on Machine Learning in Hardware Security.
ACM J. Emerg. Technol. Comput. Syst., April, 2023

Accurate and Energy-Efficient Bit-Slicing for RRAM-Based Neural Networks.
IEEE Trans. Emerg. Top. Comput. Intell., February, 2023

Severity-Based Hierarchical ECG Classification Using Neural Networks.
IEEE Trans. Biomed. Circuits Syst., February, 2023

A Lightweight Architecture for Real-Time Neuronal-Spike Classification.
CoRR, 2023

On the Reliability of RRAM-Based Neural Networks.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

Devices and Architectures for Efficient Computing In-Memory (CIM) Design.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023

Energy-efficient Computation-In-Memory Architecture using Emerging Technologies.
Proceedings of the International Conference on Microelectronics, 2023

Dependability of Future Edge-AI Processors: Pandora's Box.
Proceedings of the IEEE European Test Symposium, 2023


Mapping-aware Biased Training for Accurate Memristor-based Neural Networks.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
Energy-efficient In-Memory Address Calculation.
ACM Trans. Archit. Code Optim., 2022

Reliability aspects of binary vector-matrix-multiplications using ReRAM devices.
Neuromorph. Comput. Eng., 2022

A Voltage-Controlled, Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs.
ACM J. Emerg. Technol. Comput. Syst., 2022

A Survey on Memory-centric Computer Architectures.
ACM J. Emerg. Technol. Comput. Syst., 2022

CONVOLVE: Smart and seamless design of smart edge processors.
CoRR, 2022

Special Session: STT-MRAMs: Technology, Design and Test.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Dealing with Non-Idealities in Memristor Based Computation-In-Memory Designs.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Energy-Efficient SNN Implementation Using RRAM-Based Computation In-Memory (CIM).
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Accelerating RRAM Testing with a Low-cost Computation-in-Memory based DFT.
Proceedings of the IEEE International Test Conference, 2022

Hierarchical Memory Diagnosis.
Proceedings of the IEEE European Test Symposium, 2022

RRAM Crossbar-Based Fault-Tolerant Binary Neural Networks (BNNs).
Proceedings of the IEEE European Test Symposium, 2022

PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory.
Proceedings of the IEEE European Test Symposium, 2022

CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
Approximate Learning and Fault-Tolerant Mapping for Energy-Efficient Neuromorphic Systems.
ACM Trans. Design Autom. Electr. Syst., 2021

SRIF: Scalable and Reliable Integrate and Fire Circuit ADC for Memristor-Based CIM Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Towards Reliable In-Memory Computing: From Emerging Devices to Post-von-Neumann Architectures.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

Low-Power Memristor-Based Computing for Edge-AI Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Detecting Random Read Faults to Reduce Test Escapes in FinFET SRAMs.
Proceedings of the 26th IEEE European Test Symposium, 2021

Intermittent Undefined State Fault in RRAMs.
Proceedings of the 26th IEEE European Test Symposium, 2021

Improving the Detection of Undefined State Faults in FinFET SRAMs.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

Perspectives on Emerging Computation-in-Memory Paradigms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Unbalanced Bit-slicing Scheme for Accurate Memristor-based Neural Network Architecture.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020
Achieving Energy Efficiency for Near-Threshold Circuits Through Postfabrication Calibration and Adaptation.
IEEE Trans. Very Large Scale Integr. Syst., 2020

2019
Resilient Energy-Constrained Microprocessor Architectures.
PhD thesis, 2019

A Comprehensive Reliability Analysis Framework for NTC Caches: A System to Device Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Testing of Neuromorphic Circuits: Structural vs Functional.
Proceedings of the IEEE International Test Conference, 2019

Test Pattern Generation for Approximate Circuits Based on Boolean Satisfiability.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Fine-Grained Energy-Constrained Microprocessor Pipeline Design.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications.
Proceedings of the IEEE International Test Conference, 2018

Reliability And Performance Challenges Of Ultra-Low Voltage Caches: A Trade-Off Analysis.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Spintronic normally-off heterogeneous system-on-chip design.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Balancing resiliency and energy efficiency of functional units in ultra-low power systems.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Post-fabrication calibration of Near-Threshold circuits for energy efficiency.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Error Propagation Aware Timing Relaxation For Approximate Near Threshold Computing.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Instruction cache aging mitigation through Instruction Set Encoding.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Maximizing Energy Efficiency in NTC by Variation-Aware Microprocessor Pipeline Optimization.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

A cross-layer approach for resiliency and energy efficiency in near threshold computing.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

A cross-layer analysis of Soft Error, aging and process variation in Near Threshold Computing.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Aging mitigation in memory arrays using self-controlled bit-flipping technique.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015


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