Grigor Tshagharyan

According to our database1, Grigor Tshagharyan authored at least 18 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
An Efficient External Memory Test Solution: Case Study for HPC Application.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Overcoming Embedded Memory Test & Repair Challenges in the Gate-All-Around Era.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

SLM Subsystem for Automotive SoC: Case Study on Path Margin Monitor.
Proceedings of the IEEE International Test Conference, 2023

Utilizing ECC Analytics to Improve Memory Lifecycle Management.
Proceedings of the IEEE International Test Conference, 2023

On-chip Electromigration Sensor for Silicon Lifecycle Management of Nanoscale VLSI.
Proceedings of the IEEE European Test Symposium, 2023

2022
Innovative Practices Track: What's Next for Automotive: Where and How to Improve Field Test and Enhance SoC Safety.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

An Efficient Test Strategy for Detection of Electromigration Impact in Advanced FinFET Memories.
Proceedings of the IEEE International Test Conference, 2022

2019
Innovative Practices on In-System Test and Reliability of Memories.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Variation-aware Fault Modeling and Test Generation for STT-MRAM.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

2018
Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications.
Proceedings of the IEEE International Test Conference, 2018

Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM.
Proceedings of the IEEE International Test Conference, 2018

Implementation of Memory Static, Coupling and Dynamic Fault Models at the Register Transfer Level.
Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

2017
An effective functional safety solution for automotive systems-on-chip.
Proceedings of the IEEE International Test Conference, 2017

Experimental study on Hamming and Hsiao codes in the context of embedded applications.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

2016
Securing test infrastructure of system-on-chips.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

2015
Impact of parameter variations on FinFET faults.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Overview study on fault modeling and test methodology development for FinFET-based memories.
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

2014
Fault modeling and test algorithm creation strategy for FinFET-based memories.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014


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