Gurgen Harutunyan

Orcid: 0000-0002-9709-8336

According to our database1, Gurgen Harutunyan authored at least 52 papers between 2005 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2023
An Efficient External Memory Test Solution: Case Study for HPC Application.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Overcoming Embedded Memory Test & Repair Challenges in the Gate-All-Around Era.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

SLM Subsystem for Automotive SoC: Case Study on Path Margin Monitor.
Proceedings of the IEEE International Test Conference, 2023

Utilizing ECC Analytics to Improve Memory Lifecycle Management.
Proceedings of the IEEE International Test Conference, 2023

On-chip Electromigration Sensor for Silicon Lifecycle Management of Nanoscale VLSI.
Proceedings of the IEEE European Test Symposium, 2023

2022
Innovative Practices Track: What's Next for Automotive: Where and How to Improve Field Test and Enhance SoC Safety.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

An Efficient Test Strategy for Detection of Electromigration Impact in Advanced FinFET Memories.
Proceedings of the IEEE International Test Conference, 2022

A Novel Protection Technique for Embedded Memories with Optimized PPA.
Proceedings of the IEEE International Test Conference, 2022

2020
Memory Physical Aware Multi-Level Fault Diagnosis Flow.
IEEE Trans. Emerg. Top. Comput., 2020

Test and Diagnosis Solution for Functional Safety.
Proceedings of the IEEE International Test Conference, 2020

Die-to-Die Testing and ECC Error Mitigation in Automotive and Industrial Safety Applications.
Proceedings of the IEEE International Test Conference, 2020

2019
Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Innovative Practices on In-System Test and Reliability of Memories.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Memory FIT Rate Mitigation Technique for Automotive SoCs.
Proceedings of the IEEE International Test Conference, 2019

2018
Innovative practices on memory test practice.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications.
Proceedings of the IEEE International Test Conference, 2018

Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM.
Proceedings of the IEEE International Test Conference, 2018

Advanced Uniformed Test Approach For Automotive SoCs.
Proceedings of the IEEE International Test Conference, 2018

Advanced ECC-Based FIT Rate Mitigation Technique for Automotive SoCs.
Proceedings of the IEEE International Test Conference, 2018

Case Study and Advanced Functional Safety Solution for Automotive SoCs.
Proceedings of the IEEE International Test Conference, 2018

2017
An effective functional safety solution for automotive systems-on-chip.
Proceedings of the IEEE International Test Conference, 2017

Advanced functional safety mechanisms for embedded memories and IPs in automotive SoCs.
Proceedings of the IEEE International Test Conference, 2017

Advanced ECC solution for automotive SoCs.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Experimental study on Hamming and Hsiao codes in the context of embedded applications.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

Automated flow for test pattern creation for IPs in SoC.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

An efficient testing methodology for embedded flash memories.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

2016
Securing test infrastructure of system-on-chips.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

Extending fault periodicity table for testing external memory faults.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

2015
Impact of parameter variations on FinFET faults.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

An effective embedded test & diagnosis solution for external memories.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Overview study on fault modeling and test methodology development for FinFET-based memories.
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

A power based memory BIST grouping methodology.
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

2014
Fault modeling and test algorithm creation strategy for FinFET-based memories.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Extending fault periodicity table for testing faults in memories under 20nm.
Proceedings of the 2014 East-West Design & Test Symposium, 2014

2013
An effective solution for building memory BIST infrastructure based on fault periodicity.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Integrating embedded test infrastructure in SRAM cores to detect aging.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

An efficient fault diagnosis and localization algorithm for Successive-Approximation Analog to Digital Converters.
Proceedings of the East-West Design & Test Symposium, 2013

Impact of process variations on read failures in SRAMs.
Proceedings of the East-West Design & Test Symposium, 2013

Application of defect injection flow for fault validation in memories.
Proceedings of the East-West Design & Test Symposium, 2013

2012
A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2011
Symmetry Measure for Memory Test and Its Application in BIST Optimization.
J. Electron. Test., 2011

Generic BIST architecture for testing of content addressable memories.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

A Robust Solution for Embedded Memory Test and Repair.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
An efficient March test for detection of all two-operation dynamic faults from subclass Sav.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

2008
An Efficient March-Based Three-Phase Fault Location and Full Diagnosis Algorithm for Realistic Two-Operation Dynamic Faults in Random Access Memories.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

2007
Minimal March Tests for Detection of Dynamic Faults in Random Access Memories.
J. Electron. Test., 2007

A March-based Fault Location Algorithm with Partial and Full Diagnosis for All Simple Static Faults in Random Access Memories.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006
Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

A March-Based Algorithm for Location and Full Diagnosis of All Unlinked Static Faults.
Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006

Minimal March Tests for Dynamic Faults in Random Access Memories.
Proceedings of the 11th European Test Symposium, 2006

Minimal March-Based Fault Location Algorithm with Partial Diagnosis for all Static Faults in Random Access Memories.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005
Minimal March Tests for Unlinked Static Faults in Random Access Memories.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005


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