Mustafa M. Shihab

According to our database1, Mustafa M. Shihab authored at least 16 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
FuncTeller: How Well Does eFPGA Hide Functionality?
Proceedings of the 32nd USENIX Security Symposium, 2023

2022
Physically and Algorithmically Secure Logic Locking with Hybrid CMOS/Nanomagnet Logic Circuits.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Secure Logic Locking with Strain-Protected Nanomagnet Logic.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
ATTEST: Application-Agnostic Testing of a Novel Transistor-Level Programmable Fabric.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

CASPER: CAD Framework for a Novel Transistor-Level Programmable Fabric.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAs.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
CAPE: A cross-layer framework for accurate microprocessor power estimation.
Integr., 2019

Energy Efficient Power Distribution on Many-Core SoC.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Extending the Lifetime of Coarse-Grained Runtime Reconfigurable FPGAs by Balancing Processing Element Usage.
Proceedings of the International Conference on Field-Programmable Technology, 2019

Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
ReveNAND: A Fast-Drift-Aware Resilient 3D NAND Flash Design.
ACM Trans. Archit. Code Optim., 2018

Towards a Cross-Layer Framework for Accurate Power Modeling of Microprocessor Designs.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

2016
Couture: Tailoring STT-MRAM for Persistent Main Memory.
Proceedings of the 4th Workshop on Interactions of NVM/Flash with Operating Systems and Workloads, 2016

2015
OpenNVM: An open-sourced FPGA-based NVM controller for low level memory characterization.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2014
Power, Energy, and Thermal Considerations in SSD-Based I/O Acceleration.
Proceedings of the 6th USENIX Workshop on Hot Topics in Storage and File Systems, 2014


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