Na Yan

Orcid: 0000-0001-7012-404X

Affiliations:
  • Fudan University, Shanghai, China


According to our database1, Na Yan authored at least 49 papers between 2010 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2025
A 0.2-19GHz Zero-IF Reconfigurable Quadrature Transmitter With T-Coil Matching Network.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2025

A 5-18-GHz Reconfigurable Quadrature Receiver With Enhanced I-Q Isolation and 100-500-MHz Baseband Bandwidth.
IEEE J. Solid State Circuits, August, 2025

Systematic Design of a 3.5 GS/s 11-bit Time-Interleaved SAR ADC in 28 nm CMOS Achieving 54 dB SNDR at Nyquist Frequency.
IEEE Trans. Circuits Syst. I Regul. Pap., June, 2025

A 25-31-GHz Compact True Power Detector With >33-dB Dynamic Range and Intrinsic Phase Offset Compensation in 40-nm Bulk CMOS.
IEEE J. Solid State Circuits, May, 2025

An All-Digital Spread-Spectrum Clock Generator With Feedforward Gain Calibration for LPWAN Chirp Transmission System.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2025

Design and Analysis of a 26-32-GHz 6-bit Passive Vector Modulation Phase Shifter for CMOS Bidirectional Transceiver.
IEEE Trans. Very Large Scale Integr. Syst., March, 2025

A 2 MHz-BW 80.6 dB-SNDR 95.9 dB-SFDR 2nd-order noise-shaping SAR using open-loop Gm-R amplifier.
Microelectron. J., 2025

A 12-bit 2GS/s current-steering DAC with 27 mW power consumption in 28 nm CMOS.
Microelectron. J., 2025

A 17.7-to-29.5GHz Transceiver Front-End with 3.3dB NF and 20.2dBm OP1dB in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

19.11 A 13GHz Charge-Pump PLL Achieving 15.8fs<sub>rms</sub> Integrated Jitter and -98.5dBc Reference Spur.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2024
Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low Reference Spur.
IEEE Trans. Circuits Syst. I Regul. Pap., August, 2024

A 10-bit 563-fs Step Constant-Slope Digital-to-Time Converter in 40-nm CMOS With Nonlinearity Cancellation and Range Extension Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024

5.1 A 5-to-16GHz Reconfigurable Quadrature Receiver with 50% Duty-Cycle LO and IQ-Leakage Suppression.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

An 8-14GHz 180fs-rms DTC-Less Fractional ADPLL with ADC-Based Direct Phase Digitization in 40nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023
A 6-12 GHz Wideband Low-Noise Amplifier With 0.8-1.5 dB NF and ±0.75 dB Ripple Enabled by the Capacitor Assisting Triple-Winding Transformer.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023

Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9-14.3-GHz 85-fs-rms Jitter PLL.
IEEE J. Solid State Circuits, 2023

A 26-30GHz Digitally-Controlled Variable Gain Power Amplifier with Phase Compensation and Third Order Nonlinearity Cancellation Technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

Analysis and Modeling of Non-ideal Effects in SAR ADC.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

A Vernier Time-to-Digital Converter with 1.5ps Resolution for an All-Digital Phase Locked Loop in 28nm CMOS.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

An ADPLL Design Model Based on LoRa IoT Application.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

A High Speed, Low Power and Low Phase Noise Divider for Wideband Application.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022
A 15-Bit Quadrature Digital Power Amplifier With Transformer-Based Complex-Domain Efficiency Enhancement.
IEEE J. Solid State Circuits, 2022

A Highly Integrated Passive Wireless Sensing System With Synchronized Data Streaming of Multiple Tags.
IEEE Internet Things J., 2022

A 6-18GHz Low-Noise Amplifier Using Noise Canceling Technique in 130-nm CMOS PD-SOI.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

2020
A Broadband Switched-Transformer Digital Power Amplifier for Deep Back-Off Efficiency Enhancement.
IEEE J. Solid State Circuits, 2020

A Gesture Air-Writing Tracking Method that Uses 24 GHz SIMO Radar SoC.
IEEE Access, 2020

2019
A Compact Transformer-Combined Polar/Quadrature Reconfigurable Digital Power Amplifier in 28-nm Logic LP CMOS.
IEEE J. Solid State Circuits, 2019

A temperature sensor with glucose sensor interface based on configurable incremental sigma delta ADC.
IEICE Electron. Express, 2019

A Low Power All-Digital PLL With -40dBc In-Band Fractional Spur Suppression for NB-IoT Applications.
IEEE Access, 2019

2018
A 3.22-5.45 GHz and 199 dBc/Hz FoMT CMOS Complementary Class-C DCO.
Wirel. Commun. Mob. Comput., 2018

A Low Power Impedance Transparent Receiver with Linearity Enhancement Technique for IoT Applications.
Wirel. Commun. Mob. Comput., 2018

An Active Tag Using Carrier Recovery Circuit for EPC Gen2 Passive UHF RFID Systems.
IEEE Trans. Ind. Electron., 2018

A Low-Power OFDM-Based Wake-Up Mechanism for IoE Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

An LDO regulated DC-DC converter with voltage ripple suppression and adaptive dropout voltage control.
IEICE Electron. Express, 2018

2017
A High-Efficiency Split-Merge Charge Pump for Solar Energy Harvesting.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A 3.2-to-4.6 GHz fast-settling all-digital PLL with feed forward frequency presetting.
IEICE Electron. Express, 2017

2016
A low power high sensitivity RF power detector for multi-mode active tags.
Proceedings of the IEEE International Conference on RFID Technology and Applications, 2016

2015
A high-efficiency rectifier for passive UHF RFID with wide incident power range.
IEICE Electron. Express, 2015

A fully logic CMOS compatible non-volatile memory for low power IoT applications.
Proceedings of the 5th International Conference on the Internet of Things, 2015

2014
A digital intensive clock recovery circuit for HF-Band active RFID tag.
IEICE Electron. Express, 2014

2013
A Multi-Band Low-Noise Transmitter With Digital Carrier Leakage Suppression and Linearity Enhancement.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2012
A triple-band flexible low-noise transmitter with linearity enhancement.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Ultra-Low Power Truly Random Number Generator for RFID Tag.
Wirel. Pers. Commun., 2011

A wide tuning range low-pass Gm-C filter for multi-mode wireless receivers with automatic frequency calibration.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A 0.8ps minimum-resolution sub-exponent TDC for ADPLL in 0.13µm CMOS.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A 0.6 ppm/°C current-mode bandgap with second-order temperature compensation.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A subthreshold MOSFET bandgap reference with ultra-low power supply voltage.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Power amplifier driver for SDR transmitter with high gain tuning range and dynamic power control.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
A semi-passive UHF RFID tag with on-chip temperature sensor.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010


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