Nirmal R. Saxena

According to our database, Nirmal R. Saxena authored at least 42 papers between 1986 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Characterizing and Mitigating Soft Errors in GPU DRAM.

Michael B. Sullivan, Nirmal R. Saxena, Mike O'Connor, Donghyuk Lee, Paul Racunas, Saurabh Hukerikar, Timothy Tsai, Siva Kumar Sastry Hari, Stephen W. Keckler

IEEE Micro, 2022

Error Model (EM) - A New Way of Doing Fault Simulation.

Nirmal R. Saxena, Atieh Lotfi

Proceedings of the IEEE International Test Conference, 2022

Runtime Fault Diagnostics for GPU Tensor Cores.

Saurabh Hukerikar, Nirmal R. Saxena

Proceedings of the IEEE International Test Conference, 2022

2020

On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors.

Richard Bramley, Yanxiang Huang, Guangshan Duan, Nirmal R. Saxena, Paul Racunas

Proceedings of the IEEE International Test Conference, 2020

2019

Resiliency of automotive object detection networks on GPU architectures.

Atieh Lotfi, Saurabh Hukerikar, Keshav Balasubramanian, Paul Racunas, Nirmal R. Saxena, Richard Bramley, Yanxiang Huang

Proceedings of the IEEE International Test Conference, 2019

2018

Keynote 1: The road to resilient computing in autonomous driving is paved with redundancy.

Nirmal R. Saxena, Sanu Mathew, Krishna Saraswat

Proceedings of the IEEE International Reliability Physics Symposium, 2018

Low Overhead Tag Error Mitigation for GPU Architectures.

Atieh Lotfi, Nirmal R. Saxena, Richard Bramley, Paul Racunas, Philip P. Shirvani

Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2018

2008

How Many Test Patterns are Useless?

François-Fabien Ferhani, Nirmal R. Saxena, Edward J. McCluskey, Phil Nigh

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

2004

Efficient Design Diversity Estimation for Combinational Circuits.

Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey

IEEE Trans. Computers, 2004

Reconfigurable Architecture for Autonomous Self-Repair.

Subhasish Mitra, Wei-Je Huang, Nirmal R. Saxena, Shu-Yi Yu, Edward J. McCluskey

IEEE Des. Test Comput., 2004

2002

A Design Diversity Metric and Analysis of Redundant Systems.

Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey

IEEE Trans. Computers, 2002

2001

Techniques for Estimation of Design Diversity for Combinational Logic Circuits.

Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey

Proceedings of the 2001 International Conference on Dependable Systems and Networks (DSN 2001) (formerly: FTCS), 2001

2000

Software-implemented EDAC protection against SEUs.

Philip P. Shirvani, Nirmal R. Saxena, Edward J. McCluskey

IEEE Trans. Reliab., 2000

Common-mode failures in redundant VLSI systems: a survey.

Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey

IEEE Trans. Reliab., 2000

Dependable Computing and Online Testing in Adaptive and Configurable Systems.

Nirmal R. Saxena, Santiago Fernández-Gomez, Wei-Je Huang, Subhasish Mitra, Shu-Yi Yu, Edward J. McCluskey

IEEE Des. Test Comput., 2000

Fault Escapes in Duplex Systems.

Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

An ACS Robotic Control Algorithm with Fault Tolerant Capabilities.

Shu-Yi Yu, Nirmal R. Saxena, Edward J. McCluskey

Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

A Reliable LZ Data Compressor on Reconfigurable Coprocessors.

Wei-Je Huang, Nirmal R. Saxena, Edward J. McCluskey

Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1999

Finite state machine synthesis with concurrent error detection.

Chaohuang Zeng, Nirmal R. Saxena, Edward J. McCluskey

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

A design diversity metric and reliability analysis for redundant systems.

Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998

Dependable adaptive computing systems-the ROAR project.

Nirmal R. Saxena, Edward J. McCluskey

Proceedings of the IEEE International Conference on Systems, Man and Cybernetics, 1998

1997

Parallel Signatur Analysis Design with Bounds on Aliasing.

Nirmal R. Saxena, Edward J. McCluskey

IEEE Trans. Computers, 1997

1996

Counting Two-State Transition-Tour Sequences.

Nirmal R. Saxena, Edward J. McCluskey

IEEE Trans. Computers, 1996

Generation of Test Cases for Hardware Design Verification of a Super-Scalar Fetch Processor.

Irith Pomeranz, Nirmal R. Saxena, Richard Reeve, Paritosh Kulkarni, Yan A. Li

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1995

Fault-Tolerant Features in the HaL Memory Management Unit.

Nirmal R. Saxena, David Chih-Wei Chang, Kevin Dawallu, Jaspal Kohli, Pat Helland

IEEE Trans. Computers, 1995

Floating Point Fault Tolerance with Backward Error Assertions.

Daniel Boley, Gene H. Golub, Samy Makar, Nirmal R. Saxena, Edward J. McCluskey

IEEE Trans. Computers, 1995

Design Verification of a Super-Scalar RISC Processor.

Babu Turumella, Aiman Kabakibo, Manjunath Bogadi, Karakunakara Menon, Shaleah Thusoo, Long Nguyen, Nirmal R. Saxena, Michael Chow

Proceedings of the Digest of Papers: FTCS-25, 1995

Error Detection and Handling in a Superscalar, Speculative Out-of-Order Execution Processor System.

Nirmal R. Saxena, Chien Chen, Ravi Swami, Hideki Osone, Shalesh Thusoo, David Lyon, David Chang, Anand Dharmaraj, Niteen Patkar, Yizhi Lu, Ben Chia

Proceedings of the Digest of Papers: FTCS-25, 1995

1994

Linear Complexity Assertions for Sorting.

Nirmal R. Saxena, Edward J. McCluskey

IEEE Trans. Software Eng., 1994

HALSIM - a very fast SPARC V9 behavioral model.

David R. Barach, Jaspal Kohli, John Slice, Marc Spaulding, Rajeev Bharadhwaj, Don Hudson, Cliff Neighbors, Nirmal R. Saxena, Rolland Crunk

SIGARCH Comput. Archit. News, 1994

1993

Algorithmic Synthesis of High Level Tests for Data Path Designs.

Nirmal R. Saxena, Ravi Tangirala, Ajay Srivastava

Proceedings of the Digest of Papers: FTCS-23, 1993

Concurrent Error Detection/Correction in the HAL MMU Chip.

David Chih-Wei Chang, Nirmal R. Saxena

Proceedings of the Digest of Papers: FTCS-23, 1993

1992

Simple Bounds on Serial Signature Analysis Aliasing for Random Testing.

Nirmal R. Saxena, Piero Franco, Edward J. McCluskey

IEEE Trans. Computers, 1992

1991

Refined Bounds on Signature Analysis Aliasing for Random Testing.

Nirmal R. Saxena, Piero Franco, Edward J. McCluskey

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Bounds on Signature Analysis Aliasing for Random Testing.

Nirmal R. Saxena, Piero Franco, Edward J. McCluskey

Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991

1990

Analysis of Checksums, Extended-Precision Checksums, and Cyclic Redundancy Checks.

Nirmal R. Saxena, Edward J. McCluskey

IEEE Trans. Computers, 1990

Control-Flow Checking Using Watchdog Assists and Extended-Precision Checksums.

Nirmal R. Saxena, Edward J. McCluskey

IEEE Trans. Computers, 1990

1989

Arithmetic and galois checksums.

Nirmal R. Saxena, Edward J. McCluskey

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988

Syndrome and transition count are uncorrelated.

Nirmal R. Saxena, John P. Robinson

IEEE Trans. Inf. Theory, 1988

Simultaneous signature and syndrome compression.

John P. Robinson, Nirmal R. Saxena

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

1987

A Unified View of Test Compression Methods.

John P. Robinson, Nirmal R. Saxena

IEEE Trans. Computers, 1987

1986

Accumulator Compression Testing.

Nirmal R. Saxena, John P. Robinson

IEEE Trans. Computers, 1986