Kodai Ueyoshi

According to our database, Kodai Ueyoshi authored at least 19 papers between 2016 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge.

Pouya Houshmand, Giuseppe Maria Sarda, Vikram Jain, Kodai Ueyoshi, Ioannis A. Papistas, Man Shi, Qilin Zheng, Debjyoti Bhattacharjee, Arindam Mallik, Peter Debacker, Diederik Verkest, Marian Verhelst

IEEE J. Solid State Circuits, 2023

2022

DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC.

Kodai Ueyoshi, Ioannis A. Papistas, Pouya Houshmand, Giuseppe Maria Sarda, Vikram Jain, Man Shi, Qilin Zheng, Juan Sebastian Piedrahita Giraldo, Peter Vrancx, Jonas Doevenspeck, Debjyoti Bhattacharjee, Stefan Cosemans, Arindam Mallik, Peter Debacker, Diederik Verkest, Marian Verhelst

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021

A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS.

Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020

A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes.

Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS.

Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura

IEEE J. Solid State Circuits, 2019

Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks.

Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura

IEICE Trans. Inf. Syst., 2019

2018

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W.

Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura

IEEE J. Solid State Circuits, 2018

Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators.

Takumi Kudo, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Ryota Uematsu, Yuka Oba, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki

Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS.

Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware.

Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura

Proceedings of the International Conference on Field-Programmable Technology, 2018

2017

Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation.

Takao Marukame, Kodai Ueyoshi, Tetsuya Asai, Masato Motomura, Alexandre Schmid, Masamichi Suzuki, Yusuke Higashi, Yuichiro Mitani

IEEE Trans. Circuits Syst. II Express Briefs, 2017

Quantization Error-Based Regularization in Neural Networks.

Kazutoshi Hirose, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki

Proceedings of the Artificial Intelligence XXXIV, 2017

In-memory area-efficient signal streaming processor design for binary neural networks.

Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Live demonstration: Feature extraction system using restricted Boltzmann machines on FPGA.

Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Exploring optimized accelerator design for binarized convolutional neural networks.

Kodai Ueyoshi, Kota Ando, Kentaro Orimo, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Logarithmic Compression for Memory Footprint Reduction in Neural Network Training.

Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura

Proceedings of the Fifth International Symposium on Computing and Networking, 2017

Accelerating deep learning by binarized hardware.

Shinya Takamaeda-Yamazaki, Kodai Ueyoshi, Kota Ando, Ryota Uematsu, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

Proceedings of the 2017 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2017

2016

FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting.

Kentaro Orimo, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in Deep Belief Network.

Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016