Ramon Fernandes

Orcid: 0000-0001-8781-8056

According to our database1, Ramon Fernandes authored at least 22 papers between 2013 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2021
Subutai: Speeding Up Legacy Parallel Applications Through Data Synchronization.
IEEE Trans. Parallel Distributed Syst., 2021

Using curved angular intra-frame prediction to improve video coding efficiency.
J. Vis. Commun. Image Represent., 2021

2020
Using Smart Routing for Secure and Dependable NoC-Based MPSoCs.
IEEE/ACM Trans. Netw., 2020

3D-HEVC Bipartition Modes Encoder and Decoder Design Targeting High-Resolution Videos.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Multicore Parallelism Exploration Targeting 3D-HEVC Intra-Frame Prediction.
IEEE Des. Test, 2020

2018
DCDM-Intra: Dynamically Configurable 3D-HEVC Depth Maps Intra-Frame Prediction Algorithm.
Proceedings of the 2018 IEEE International Conference on Image Processing, 2018

Low Area Reconfigurable Architecture for 3D-HEVC DMMs Decoder Targeting 1080p Videos.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Least-Squares Approximation Surfaces for High Quality Intra-Frame Prediction in Future Video Standards.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Subutai: distributed synchronization primitives in NoC interfaces for legacy parallel-applications.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
A security-aware routing implementation for dynamic data protection in zone-based MPSoC.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

2016
A security aware routing approach for NoC-based MPSoCs.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Architectural exploration of Last-Level Caches targeting homogeneous multicore systems.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Towards risk aware NoCs for data protection in MPSoCs.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

3D-HEVC depth maps intra prediction complexity analysis.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Evaluation of emerging TSV-enabled main memories on the PARSEC benchmark.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
OcNoC: Efficient One-Cycle Router Implementation for 3D Mesh Network-on-Chip.
Proceedings of the 28th International Conference on VLSI Design, 2015

Smart Reconfiguration Approach for Fault-Tolerant NoC Based MPSoCs.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

Task partitioning optimization algorithm for energy saving and load balance on NoC-based MPSoCs.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

A non-intrusive and reconfigurable access control to secure NoCs.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014
Tiny NoC: A 3D Mesh Topology with Router Channel Optimization for Area and Latency Minimization.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

The impact of routing arbitration mechanisms on 3D NoC latency.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
A flexible framework for modeling and simulation of multipurpose wireless networks.
Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013


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