Riko Radojcic

According to our database1, Riko Radojcic authored at least 14 papers between 2005 and 2013.

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Bibliography

2013
Power and signal integrity challenges in 3D systems.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2012

3D stacking: Where the rubber meets the road.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

Roadmap for design and EDA infrastructure for 3D products.
Proceedings of the 2012 IEEE Hot Chips 24 Symposium (HCS), 2012

2010
3-D stacked die: now or future?
Proceedings of the 47th Design Automation Conference, 2010

Simulation methodology and flow integration for 3D IC stress management.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Enabling power distribution network analysis flows for 3D ICs.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
Pathfinding: A design methodology for fast exploration and optimisation of 3D-stacked integrated circuits.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

Moore's Law: another casualty of the financial meltdown?
Proceedings of the 46th Design Automation Conference, 2009

Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
Holistic pathfinding: virtual wireless chip design for advanced technology and design exploration.
Proceedings of the 45th Design Automation Conference, 2008

2007
Integration of CMP Modeling in RC Extraction and Timing Flow.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Variation-aware analysis: savior of the nanometer era?
Proceedings of the 43rd Design Automation Conference, 2006

2005
Are there economic benefits in DFM?
Proceedings of the 42nd Design Automation Conference, 2005


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