Robert J. Sonnelitter

According to our database, Robert J. Sonnelitter authored at least 10 papers between 2013 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

The IBM Telum II Processor.

Christopher J. Berry, Michael J. Becht, Tim E. Bubb, Howard Haynie, Robert J. Sonnelitter, Katie Seggerman, Jonathan Hsieh, Edward Malley, Mike Cadigan, Susan M. Eickhoff, Matthias Klein, Craig R. Walters, Christian G. Zoellin, Cédric Lichtenau

IEEE Micro, 2025

2.2 IBM Telum II: Next Generation 5.5GHz Microprocessor with On-Die Data Processing Unit and Improved AI Accelerator.

Gerald Strevig, Christopher J. Berry, Rahul M. Rao, Noam Jungmann, Michael A. Sperling, Michael J. Becht, Eduard Herkel, Matthias Pflanz, Patrick J. Meaney, Michael Romain, Mark Cichanowski, Amanda Venton, David Wolpert, Elazar Kachir, Luke Hopkins, Tim E. Bubb, Andreas Arp, Daniel Kiss, Simon Büchsenstein, Michael H. Wood, Michael Spear, Robert J. Sonnelitter, Rajiv Joshi

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

Enterprise Class Modular Cache Hierarchy.

Craig R. Walters, Deanna Postles Dunn Berger, Robert J. Sonnelitter, Alper Buyuktosunoglu

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025

2023

Enterprise-Class Multilevel Cache Design: Low Latency, Huge Capacity, and High Reliability.

Deanna Postles Dunn Berger, Christian Jacobi, Craig R. Walters, Robert J. Sonnelitter, Mike Cadigan, Matthias Klein

IEEE Micro, 2023

2022

IBM Telum: a 16-Core 5+ GHz DCM.

Ofer Geva, Christopher J. Berry, Robert J. Sonnelitter, David Wolpert, Adam Collura, Thomas Strach, Di Phan, Cédric Lichtenau, Alper Buyuktosunoglu, Hubert Harrer, Jeffrey A. Zitz, Chad Marquart, Douglas Malone, Tobias Webel, Adam Jatkowski, John Isakson, Dina Hamid, Mark Cichanowski, Michael Romain, Faisal Hasan, Kevin Williams, Jesse Surprise, Chris Cavitt, Mark Cohen

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2020

Design of the IBM z15 microprocessor.

Anthony Saporito, Martin Recktenwald, Christian Jacobi, Gerrit Koch, Deanna Postles Dunn Berger, Robert J. Sonnelitter, Craig R. Walters, Jang-Soo Lee, Cédric Lichtenau, Ulrich Mayer, Eduard Herkel, Stefan Payer, Silvia M. Müller, Vesselina K. Papazova, Ekaterina M. Ambroladze, Timothy C. Bronson

IBM J. Res. Dev., 2020

2018

Design of the IBM z14 microprocessor.

Christian Jacobi, Anthony Saporito, Martin Recktenwald, Aaron Tsai, Ulrich Mayer, Markus M. Helms, Adam Collura, Pak-kin Mak, Robert J. Sonnelitter, Michael A. Blake, Tim Bronson, Arthur O'neill, Vesselina K. Papazova

IBM J. Res. Dev., 2018

IBM z14™: 14nm microprocessor for the next-generation mainframe.

Christopher J. Berry, James D. Warnock, John Isakson, John Badar, Brian Bell, Frank Malgioglio, Guenter Mayer, Dina Hamid, Jesse Surprise, David Wolpert, Ofer Geva, Bill Huott, Leon J. Sigal, Sean M. Carey, Richard F. Rizzolo, Ricardo Nigaglioni, Mark Cichanowski, Dureseti Chidambarrao, Christian Jacobi, Anthony Saporito, Arthur O'neill, Robert J. Sonnelitter, Christian G. Zoellin, Michael H. Wood, José Neves

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2015

The IBM z13 processor cache subsystem.

Craig R. Walters, Pak-kin Mak, Deanna Postles Dunn Berger, Michael A. Blake, Tim Bronson, K. D. Klapproth, A. J. O'Neill, Robert J. Sonnelitter, Vesselina K. Papazova

IBM J. Res. Dev., 2015

2013

IBM zEC12 processor subsystem.

Robert J. Sonnelitter

Proceedings of the 2013 IEEE Hot Chips 25 Symposium (HCS), 2013