Rohan Sinha

According to our database, Rohan Sinha authored at least 14 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Voltage Mode Charge Pump Regulator with Improved Compensation and Dynamic Body Biasing Scheme.

Rohan Sinha, Devraj M. Rajagopal, Aditya Madhavan

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023

Semantic anomaly detection with large language models.

Amine Elhafsi, Rohan Sinha, Christopher Agia, Edward Schmerling, Issa A. D. Nesnas, Marco Pavone

Auton. Robots, December, 2023

A Temperature Compensated Voltage Controlled Relaxation Oscillator for Frequency Modulated DC-DC Charge Pump Regulation.

Rohan Sinha, Devraj M. Rajagopal, Niharika Khare

IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

Closing the Loop on Runtime Monitors with Fallback-Safe MPC.

Rohan Sinha, Edward Schmerling, Marco Pavone

Proceedings of the 62nd IEEE Conference on Decision and Control, 2023

2022

A System-Level View on Out-of-Distribution Data in Robotics.

Rohan Sinha, Apoorva Sharma, Somrita Banerjee, Thomas Lew, Rachel Luo, Spencer M. Richards, Yixiao Sun, Edward Schmerling, Marco Pavone

CoRR, 2022

Adaptive Robust Model Predictive Control via Uncertainty Cancellation.

Rohan Sinha, James Harrison, Spencer M. Richards, Marco Pavone

CoRR, 2022

Online Distribution Shift Detection via Recency Prediction.

Rachel Luo, Rohan Sinha, Ali Hindy, Shengjia Zhao, Silvio Savarese, Edward Schmerling, Marco Pavone

CoRR, 2022

An Accurate Modelling of CMOS Folded Cascode Op-Amp with Negative Transconductance.

B. Krishnanunni, Devraj M. Rajagopal, Rohan Sinha

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Adaptive Robust Model Predictive Control with Matched and Unmatched Uncertainty.

Rohan Sinha, James Harrison, Spencer M. Richards, Marco Pavone

Proceedings of the American Control Conference, 2022

2020

A 0.8V Input Charge Pump Circuit with PVT Aware Body Bias Clock Drivers for Powering Non-Volatile Memories.

Rohan Sinha, Rajat Kulshrestha, Vinay N. D

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2018

Stress Relaxed Multiple Output High-Voltage Level Shifter.

Vikas Rana, Rohan Sinha

IEEE Trans. Circuits Syst. II Express Briefs, 2018

2015

Analysis of stability and different speed boosting assist techniques towards the design and optimization of high speed SRAM cell.

Rohan Sinha, Pranay Samanta

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

A new row decoding architecture for fast wordline charging in NOR type Flash memories.

Rohan Sinha, Bhawana Singh Nirwan, Mohammad S. Hashmi

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2014

A positive level shifter for high speed symmetric switching in flash memories.

Rohan Sinha, Mohammad S. Hashmi, G. Anil Kumar

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014