Sachin Taneja
Orcid: 0000-0002-4590-7875
According to our database1,
Sachin Taneja
authored at least 24 papers
between 2015 and 2025.
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Bibliography
2025
A 4.7-to-5.3-Gb/s Fault-Injection and Side-Channel Attack-Resistant AES-256 Engine Using Masked Isomorphic Composite Fields in Intel 4 CMOS.
IEEE J. Solid State Circuits, April, 2025
A 2455μm<sup>2</sup> 1.7Gbps Side-Channel Attack-Resistant Masked HMAC-SHA256 Accelerator in Intel 4 CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
2024
A 100-Gbps Fault-Injection Attack-Resistant AES-256 Engine With 99.1%-99.99% Error Coverage in Intel 4 CMOS.
IEEE J. Solid State Circuits, January, 2024
A 4.7-to-5.3Gbps Fault-Injection Attack Resistant AES-256 Engine Using Isomorphic Composite Fields in Intel 4 CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024
2023
IEEE J. Solid State Circuits, 2023
218Kauth/s, 3nJ/auth SCA/ML-Resistant Privacy-Preserving Mutual Authentication Accelerator with a Crypto-Double-Coupled PUF in 4nm class CMOS.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 100Gbps Fault-Injection Attack Resistant AES-256 Engine with 99.1-to-99.99% Error Coverage in Intel 4 CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
IEEE J. Solid State Circuits, 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
IEEE J. Solid State Circuits, 2021
PUF Architecture with Run-Time Adaptation for Resilient and Energy-Efficient Key Generation via Sensor Fusion.
IEEE J. Solid State Circuits, 2021
36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm<sup>2</sup> and 749-1, 459 TOPS/W in 28nm.
Proceedings of the 47th ESSCIRC 2021, 2021
2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
Token-Based Security for the Internet of Things With Dynamic Energy-Quality Tradeoff.
IEEE Internet Things J., 2019
PUF-based Key Generation with Design Margin Reduction via In-Situ and PVT Sensor Fusion.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
Enabling Ubiquitous Hardware Security via Energy-Efficient Primitives and Systems : (Invited Paper).
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm.
IEEE J. Solid State Circuits, 2018
Ultra-Low Power Crypto-Engine Based on Simon 32/64 for Energy- and Area-Constrained Integrated Systems.
CoRR, 2018
2017
A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8-1.0V in 40nm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2015
A 128-kb 10% power reduced 1T high density ROM with 0.56 ns access time using bitline edge sensing in sub 16nm bulk FinFET technology.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015