Kaviraj Chopra

According to our database1, Kaviraj Chopra authored at least 22 papers between 2004 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2011
Process Variation and Temperature-Aware Full Chip Oxide Breakdown Reliability Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Fast Statistical Static Timing Analysis Using Smart Monte Carlo Techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010
Victim Alignment in Crosstalk-Aware Timing Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2008
Statistical Performance Analysis Optimization of Digital Circuits.
PhD thesis, 2008

A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Statistical Timing Analysis: From Basic Principles to State of the Art.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A statistical approach for full-chip gate-oxide reliability analysis.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Transistor-Specific Delay Modeling for SSTA.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Victim alignment in crosstalk aware timing analysis.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Top-k Aggressors Sets in Delay Noise Analysis.
Proceedings of the 44th Design Automation Conference, 2007

2006
Efficient Symbolic Algorithms for Computing the Minimum and Bounded Leakage States.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Analysis and modeling of CD variation for statistical static timing.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A new statistical max operation for propagating skewness in statistical timing analysis.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

An efficient static algorithm for computing the soft error rates of combinational circuits.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Statistical Timing Based Optimization using Gate Sizing.
Proceedings of the 2005 Design, 2005

CAD tools for variation tolerance.
Proceedings of the 42nd Design Automation Conference, 2005

Circuit optimization using statistical static timing analysis.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A Framework for Battery-Aware Sensor Management.
Proceedings of the 2004 Design, 2004

Implicit pseudo boolean enumeration algorithms for input vector control.
Proceedings of the 41th Design Automation Conference, 2004


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