Sean Eilert

Orcid: 0000-0002-5378-2961

According to our database1, Sean Eilert authored at least 10 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
In-Memory Versioning (IMV).
IEEE Comput. Archit. Lett., 2023

2022
To PIM or not for emerging general purpose processing in DDR memory systems.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

SALIENT: Ultra-Fast FPGA-based Short Read Alignment.
Proceedings of the International Conference on Field-Programmable Technology, 2022

FAST: FPGA-based Acceleration of Genomic Sequence Trimming.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022

2021
FPRA: A Fine-grained Parallel RRAM Architecture.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

Design space for scaling-in general purpose computing within the DDR DRAM hierarchy for map-reduce workloads.
Proceedings of the CF '21: Computing Frontiers Conference, 2021

2020
Fulcrum: A Simplified Control and Access Mechanism Toward Flexible and Practical In-Situ Accelerators.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

2018
Energy-Efficient Deep In-memory Architecture for NAND Flash Memories.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2014
DataCenter 2020: Near-memory acceleration for data-oriented applications.
Proceedings of the Symposium on VLSI Circuits, 2014

An energy-efficient VLSI architecture for pattern recognition via deep embedding of computation in SRAM.
Proceedings of the IEEE International Conference on Acoustics, 2014


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