Sebastian Huhn
Orcid: 0000-0001-6950-7967Affiliations:
- University of Bremen, Institute of Computer Science, Germany
According to our database1,
Sebastian Huhn
authored at least 25 papers
between 2016 and 2023.
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Bibliography
2023
A Novel LBIST Signature Computation Method for Automotive Microcontrollers using a Digital Twin.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization Operators for On-Chip Transient Fault Detection.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022
Next Generation Design For Testability, Debug and Reliability Using Formal Techniques.
Proceedings of the IEEE International Test Conference, 2022
Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods.
Proceedings of the IEEE European Test Symposium, 2022
2021
Optimization-based Test Scheduling for IEEE 1687 Multi-Power Domain Networks Using Boolean Satisfiability.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021
A Codeword-based Compactor for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
2020
Next generation design for testability, debug and reliability using formal techniques.
PhD thesis, 2020
Combining Machine Learning and Formal Techniques for Small Data Applications - A Framework to Explore New Structural Materials.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
2019
Determining Application-Specific Knowledge for Improving Robustness of Sequential Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2019
A Hybrid Embedded Multichannel Test Compression Architecture for Low-Pin Count Test Environments in Safety-Critical Systems.
Proceedings of the IEEE International Test Conference in Asia, 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019
2018
Building Fast Multi Agent Systems Using Hardware Design Languages for High-Throughput Systems.
Proceedings of the Dynamics in Logistics, 2018
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
2017
Revealing properties of structural materials by combining regression-based algorithms and nano indentation measurements.
Proceedings of the 2017 IEEE Symposium Series on Computational Intelligence, 2017
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Enhancing robustness of sequential circuits using application-specific knowledge and formal methods.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
Exploring superior structural materials using multi-objective optimization and formal techniques.
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016
Proceedings of the 21th IEEE European Test Symposium, 2016