Stephan Eggersglüß
Orcid: 0000-0002-5698-9132Affiliations:
- Siemens Digital Industries Software, Wilsonville, OR, USA
- DFKI, Bremen (former)
According to our database1,
Stephan Eggersglüß
authored at least 54 papers
between 2007 and 2023.
Collaborative distances:
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Bibliography
2023
IEEE Trans. Very Large Scale Integr. Syst., April, 2023
2021
Proceedings of the IEEE International Test Conference, 2021
2019
Cluster-based Localization of IR-drop in Test Application considering Parasitic Elements.
Proceedings of the IEEE Latin American Test Symposium, 2019
Proceedings of the IEEE International Test Conference, 2019
Towards Complete Fault Coverage by Test Point Insertion using Optimization-SAT Techniques.
Proceedings of the IEEE International Test Conference in Asia, 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
2018
Constraint-Based Pattern Retargeting for Reducing Localized Power Activity During Testing.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
Revealing properties of structural materials by combining regression-based algorithms and nano indentation measurements.
Proceedings of the 2017 IEEE Symposium Series on Computational Intelligence, 2017
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
Machine learning based test pattern analysis for localizing critical power activity areas.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Identification of Efficient Clustering Techniques for Test Power Activity on the Layout.
Proceedings of the 26th IEEE Asian Test Symposium, 2017
2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Exploring superior structural materials using multi-objective optimization and formal techniques.
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016
Proceedings of the 21th IEEE European Test Symposium, 2016
SAT-based post-processing for regional capture power reduction in at-speed scan test generation.
Proceedings of the 21th IEEE European Test Symposium, 2016
Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test.
Proceedings of the 25th IEEE Asian Test Symposium, 2016
2015
Proceedings of the 20th IEEE European Test Symposium, 2015
2014
An effective fault ordering heuristic for SAT-based dynamic test compaction techniques.
it Inf. Technol., 2014
J. Electron. Test., 2014
Proceedings of the 9th International Design and Test Symposium, 2014
Proceedings of the 19th IEEE European Test Symposium, 2014
Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014
2013
Proceedings of the 14th Latin American Test Workshop, 2013
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Proceedings of the 22nd Asian Test Symposium, 2013
2012
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Springer, ISBN: 978-1-4419-9975-7, 2012
2011
Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization.
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Robust algorithms for high quality test pattern generation using Boolean satisfiability.
PhD thesis, 2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
J. Electron. Test., 2010
Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Robuste Erfüllbarkeitsalgorithmen zur Generierung hochwertiger Testmuster für digitale Schaltungen.
Proceedings of the Ausgezeichnete Informatikdissertationen 2010, 2010
Proceedings of the 15th European Test Symposium, 2010
2009
Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation).
it Inf. Technol., 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques.
Proceedings of the 14th IEEE European Test Symposium, 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
Springer, ISBN: 978-90-481-2359-9, 2009
2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008
Proceedings of the Evolutionary Test Generation, 24.08. - 29.08.2008, 2008
2007
Proceedings of the IFIP VLSI-SoC 2007, 2007
Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007
Formal Verification on the Word Level using SAT-like Proof Techniques.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 16th Asian Test Symposium, 2007