Daniel Tille

According to our database, Daniel Tille authored at least 26 papers between 2007 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Performance Screening Using Functional Path Ring Oscillators.

Tobias Kilian, Daniel Tille, Martin Huch, Markus Hanel, Ulf Schlichtmann

IEEE Trans. Very Large Scale Integr. Syst., June, 2023

A Novel LBIST Signature Computation Method for Automotive Microcontrollers using a Digital Twin.

Daniel Tille, Leon Klimasch, Sebastian Huhn

Proceedings of the 41st IEEE VLSI Test Symposium, 2023

An efficient High-Volume Production Performance Screening using On-Chip Ring Oscillators.

Tobias Kilian, Abhishek Sengupta, Daniel Tille, Martin Huch, Ulf Schlichtmann

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

2022

A Path Selection Flow for Functional Path Ring Oscillators using Physical Design Data.

Tobias Kilian, Markus Hanel, Daniel Tille, Martin Huch, Ulf Schlichtmann

Proceedings of the IEEE International Test Conference, 2022

Reducing Routing Overhead by Self-Enabling Functional Path Ring Oscillators.

Tobias Kilian, Markus Hanel, Daniel Tille, Martin Huch, Ulf Schlichtmann

Proceedings of the IEEE European Test Symposium, 2022

2021

Time and Area Optimized Testing of Automotive ICs.

Nilanjan Mukherjee, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer

IEEE Trans. Very Large Scale Integr. Syst., 2021

A Scalable Design Flow for Performance Monitors Using Functional Path Ring Oscillators.

Tobias Kilian, Heiko Ahrens, Daniel Tille, Martin Huch, Ulf Schlichtmann

Proceedings of the IEEE International Test Conference, 2021

2019

Test Time and Area Optimized BrST Scheme for Automotive ICs.

Nilanjan Mukherjee, Jerzy Tyszer, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki

Proceedings of the IEEE International Test Conference, 2019

A Hybrid Embedded Multichannel Test Compression Architecture for Low-Pin Count Test Environments in Safety-Critical Systems.

Sebastian Huhn, Daniel Tille, Rolf Drechsler

Proceedings of the IEEE International Test Conference in Asia, 2019

Hybrid Architecture for Embedded Test Compression to Process Rejected Test Patterns.

Sebastian Huhn, Daniel Tille, Rolf Drechsler

Proceedings of the 24th IEEE European Test Symposium, 2019

2018

On enabling diagnosis for 1-Pin Test fails in an industrial flow.

Daniel Tille, Benedikt Gottinger, Ulrike Pfannkuchen, Helmut Graeb, Ulf Schlichtmann

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

A lightweight X-masking scheme for IoT designs.

Daniel Tille, Benedikt Gottinger, Ulrike Pfannkuchen

Proceedings of the International Test Conference in Asia, 2017

2016

Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test.

Stephan Eggersglüß, Stefan Holst, Daniel Tille, Kohei Miyase, Xiaoqing Wen

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2014

Automated formal verification of X propagation with respect to testability issues.

Mehdi Dehbashi, Daniel Tille, Ulrike Pfannkuchen, Stephan Eggersglüß

Proceedings of the 9th International Design and Test Symposium, 2014

2010

Incremental Solving Techniques for SAT-based ATPG.

Daniel Tille, Stephan Eggersglüß, Rolf Drechsler

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation.

Stephan Eggersglüß, Daniel Tille, Rolf Drechsler

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs.

Daniel Tille, Stephan Eggersglüß, Rene Krenz-Baath, Jürgen Schlöffel, Rolf Drechsler

Proceedings of the 15th European Test Symposium, 2010

2009

Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation).

Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille

it Inf. Technol., 2009

A fast untestability proof for SAT-based ATPG.

Daniel Tille, Rolf Drechsler

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

Speeding up SAT-Based ATPG Using Dynamic Clause Activation.

Stephan Eggersglüß, Daniel Tille, Rolf Drechsler

Proceedings of the Eighteentgh Asian Test Symposium, 2009

Test Pattern Generation using Boolean Proof Engines.

Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille

Springer, ISBN: 978-90-481-2359-9, 2009

2008

On Acceleration of SAT-Based ATPG for Industrial Designs.

Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Incremental SAT Instance Generation for SAT-based ATPG.

Daniel Tille, Rolf Drechsler

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

SAT-based Automatic Test Pattern Generation.

Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille

Proceedings of the Evolutionary Test Generation, 24.08. - 29.08.2008, 2008

2007

Experimental Studies on SAT-Based ATPG for Gate Delay Faults.

Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel

Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

Instance Generation for SAT-based ATPG.

Daniel Tille, Görschwin Fey, Rolf Drechsler

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007