Toshiyuki Yamagishi

According to our database1, Toshiyuki Yamagishi authored at least 10 papers between 2011 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
An 802.11ax 4 × 4 High-Efficiency WLAN AP Transceiver SoC Supporting 1024-QAM With Frequency-Dependent IQ Calibration and Integrated Interference Analyzer.
IEEE J. Solid State Circuits, 2018

A 1024-QAM Capable WLAN Receiver with -56.3dB Image Rejection Ratio Using Self-Calibration Technique.
IEICE Trans. Electron., 2018


2017
A 1024-QAM capable WLAN receiver with -56.3 dB image rejection ratio using self-calibration technique.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2014
A 1.4Mpixel CMOS image sensor with multiple row-rescan based data sampling for optical camera communication.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
A Standard-Cell Based On-Chip NMOS and PMOS Performance Monitor for Process Variability Compensation.
IEICE Trans. Electron., 2013

2012
An area-efficient, standard-cell based on-chip NMOS and PMOS performance monitor for process variability compensation.
Proceedings of the 2012 IEEE Symposium on Low-Power and High-Speed Chips, 2012

2011
High-Throughput, Low-Power Software-Defined Radio Using Reconfigurable Processors.
IEEE Micro, 2011

A multimodal wireless baseband core using a coarse-grained dynamic reconfigurable processor.
Proceedings of the 2011 IEEE Symposium on Low-Power and High-Speed Chips, 2011

A 7uW deep-sleep, ultra low-power WLAN baseband LSI for mobile applications.
Proceedings of the 2011 IEEE Symposium on Low-Power and High-Speed Chips, 2011


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