Subhasish Mukherjee

According to our database, Subhasish Mukherjee authored at least 5 papers between 2008 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2013

Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study.

Sandeep Kumar Goel, Saman Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, Frank Lee, Vivek Chickermane, Brion L. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Hyungdong Lee, Jungi Choi, Sangdoo Kim

Proceedings of the 2013 IEEE International Test Conference, 2013

SmartScan - Hierarchical test compression for pin-limited low power designs.

Krishna Chakravadhanula, Vivek Chickermane, Don Pearl, Akhil Garg, R. Khurana, Subhasish Mukherjee, P. Nagaraj

Proceedings of the 2013 IEEE International Test Conference, 2013

2012

DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks.

Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen

Proceedings of the 2012 IEEE International Test Conference, 2012

2011

Automation of 3D-DfT Insertion.

Sergej Deutsch, Vivek Chickermane, Brion L. Keller, Subhasish Mukherjee, Mario Konijnenburg, Erik Jan Marinissen, Sandeep Kumar Goel

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2008

A Partitioning Based Physical Scan Chain Allocation Algorithm that Minimizes Voltage Domain Crossings.

Nilabha Dev, Sandeep Bhatia, Subhasish Mukherjee, Sue Genova, Vinayak Kadam

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008