Subodh M. Reddy

According to our database1, Subodh M. Reddy authored at least 8 papers between 1995 and 2011.

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Bibliography

2011
A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS.
IEEE J. Solid State Circuits, 2010

2006
Accurate Substrate Noise Analysis Based on Library Module Characterization.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Clock Distribution Architectures: A Comparative Study.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Analyzing timing uncertainty in mesh-based clock architectures.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
A sliding window scheme for accurate clock mesh analysis.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2004
Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis.
Proceedings of the 2004 Design, 2004

1995
Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment.
Proceedings of the 32st Conference on Design Automation, 1995


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