Takeshi Nakano
According to our database1,
Takeshi Nakano
authored at least 6 papers
between 2009 and 2025.
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Bibliography
2025
A 1Tb 3b/cell 3D-Flash Memory with a 29%-Improved-Energy-Efficiency Read Operation and 4.8Gb/s Power-Isolated Low-Tapped-Termination I/Os.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
2023
A 1Tb 3b/Cell 3D-Flash Memory of more than 17Gb/mm<sup>2</sup> bit density with 3.2Gbps interface and 205MB/s program throughput.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2021
Practical Learning of Science for Elementary School Students via Programming and Control Experimentation.
J. Robotics Netw. Artif. Life, 2021
2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
Proceedings of the Knowledge-Based Software Engineering: 2018, 2018
2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009