Tom Waayers

According to our database, Tom Waayers authored at least 13 papers between 2001 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2013

Industrial Application of IEEE P1687 for an Automotive Product.

Martin Keim, Tom Waayers, Richard Morren, Friedrich Hapke, Rene Krenz-Baath

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2010

Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains.

Tom Waayers, Richard Morren, Xijiang Lin, Mark Kassab

Proceedings of the 2011 IEEE International Test Conference, 2010

2005

Definition of a robust modular SOC test architecture; resurrection of the single TAM daisy-chain.

Tom Waayers, Richard Morren, Roberto Grandi

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

IEEE Std 1500 Compliant Infrastructure forModular SOC Testing.

Tom Waayers, Erik Jan Marinissen, Maurice Lousberg

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Extending the Digital Core-based Test Methodology to Support Mixed-Signal.

Geert Seuren, Tom Waayers

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Infrastructure for modular SOC testing.

Erik Jan Marinissen, Tom Waayers

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003

Multi-TAP Controller Architecture for Digital System Chips.

Bart Vermeulen, Tom Waayers, Sjaak Bakker

J. Electron. Test., 2003

An improved Test Control Architecture and Test Control Expansion for Core-Based System Chips.

Tom Waayers

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

An extension to JTAG for at-speed debug on a system.

Leon van de Logt, Frank van der Heyden, Tom Waayers

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002

Enhanced Reduced Pin-Count Test for Full-Scan Design.

Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier

J. Electron. Test., 2002

Core-Based Scan Architecture for Silicon Debug.

Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips.

Bart Vermeulen, Tom Waayers, Sjaak Bakker

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001

A P1500 Compliant Programable BistShell for Embedded Memories.

Sandeep Koranne, Tom Waayers, Robert Beurze, Clemens Wouters, Sunil Kumar, G. S. Visweswara

Proceedings of the 9th IEEE International Workshop on Memory Technology, 2001