Friedrich Hapke

According to our database1, Friedrich Hapke authored at least 33 papers between 2003 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
DPPM Reduction Methods and New Defect Oriented Test Methods Applied to Advanced FinFET Technologies.
Proceedings of the IEEE International Test Conference, 2018

Total Critical Area Based Testing.
Proceedings of the IEEE International Test Conference, 2018

2017
Bridge over troubled waters: Critical area based pattern generation.
Proceedings of the 22nd IEEE European Test Symposium, 2017

2016
On New Test Points for Compact Cell-Aware Tests.
IEEE Des. Test, 2016

Cell-aware diagnosis: Defective inmates exposed in their cells.
Proceedings of the 21th IEEE European Test Symposium, 2016

2015
Diagnosing timing related cell internal defects for FinFET technology.
Proceedings of the VLSI Design, Automation and Test, 2015

Embedded deterministic test points for compact cell-aware tests.
Proceedings of the 2015 IEEE International Test Conference, 2015

2014
Cell-Aware Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Cell-aware experiences in a high-quality automotive test suite.
Proceedings of the 19th IEEE European Test Symposium, 2014

Diagnosing Cell Internal Defects Using Analog Simulation-Based Fault Models.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Industrial Application of IEEE P1687 for an Automotive Product.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Fault collapsing of multi-conditional faults.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012
Cell-aware Production test results from a 32-nm notebook processor.
Proceedings of the 2012 IEEE International Test Conference, 2012

Introduction to the defect-oriented cell-aware test methodology for significant reduction of DPPM rates.
Proceedings of the 17th IEEE European Test Symposium, 2012

Robust Evaluation of Weighted Random Logic BIST Structures in Industrial Designs.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

A new SAT-based ATPG for generating highly compacted test sets.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

EDA solutions to new-defect detection in advanced process technologies.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Cell-aware analysis for small-delay effects and production test results from different fault models.
Proceedings of the 2011 IEEE International Test Conference, 2011

2010
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics.
J. Electron. Test., 2010

Defect-oriented cell-internal testing.
Proceedings of the 2011 IEEE International Test Conference, 2010

2009
Restrict Encoding for Mixed-Mode BIST.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs.
Proceedings of the 2009 IEEE International Test Conference, 2009

2008
On Acceleration of SAT-Based ATPG for Industrial Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2007
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults.
Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

Programmable deterministic Built-In Self-Test.
Proceedings of the 2007 IEEE International Test Conference, 2007

Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled Defects.
Proceedings of the 2007 IEEE International Test Conference, 2007

Experimental Studies on SAT-Based ATPG for Gate Delay Faults.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

2006
X-masking during logic BIST and its impact on defect coverage.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Fault detection and diagnosis with parity trees for space compaction of test responses.
Proceedings of the 43rd Design Automation Conference, 2006

2005
PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

2004
X-Masking During Logic BIST and Its Impact on Defect Coverage.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Efficient Pattern Mapping for Deterministic Logic BIST.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
ATPG Padding And ATE Vector Repeat Per Port For Reducing Test Data Volume.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003


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